Patents by Inventor Sven Albers

Sven Albers has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411000
    Abstract: A microelectronic package is described with an illuminated backside exterior. In one example, the package has a package substrate, a die attached to the package substrate, a cover over the die and the package substrate, a lamp, and a screen over the die, externally visible and optically coupled to the lamp so that when the lamp is illuminated the illumination is externally visible through the screen.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: September 10, 2019
    Assignee: Intel IP Corporation
    Inventors: Marc Stephan Dittes, Sven Albers, Christian Georg Geissler, Andreas Wolter, Klaus Reingruber, Georg Seidemann, Thomas Wagner, Richard Patten
  • Patent number: 10403609
    Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: September 3, 2019
    Assignee: Intel IP Corporation
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Patent number: 10373844
    Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: May 9, 2017
    Date of Patent: August 6, 2019
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Sonja Koller, Thorsten Meyer, Georg Seidemann, Christian Geissler, Andreas Wolter
  • Publication number: 20190206833
    Abstract: Embodiments of the invention include an eWLB or ePLB based PoP device and methods of forming such devices. According to an embodiment, such a device may include a die embedded within a mold layer. A substrate may be directly contacting a surface of the mold layer. Additionally, embodiments of the invention may include a through mold via formed through the mold layer that is electrically coupled to a contact formed on a surface of the substrate that is contacting the mold layer. In order to form such a device, embodiments may include dispensing a molding material over a die positioned on a mold carrier. Thereafter, a substrate may be pressed into the molding material. After curing the molding material, a mold layer may be formed that encases the die and is adhered to the substrate.
    Type: Application
    Filed: December 23, 2015
    Publication date: July 4, 2019
    Inventors: Thorsten MEYER, Klaus REINGRUBER, Georg SEIDEMANN, Andreas WOLTER, Christian GEISSLER, Sven ALBERS
  • Publication number: 20190121041
    Abstract: Embodiments of the disclosure are directed to a chip package that includes a base that includes a redistribution layer; an optical transducer circuit element on the base electrically connected to the redistribution layer; an optical element adjacent to the optical transducer circuit element and at an edge of the base; and an encasement encasing the optical transducer circuit element and a portion of the optical element, wherein one side of the optical element is exposed at an edge of the encasement and at the edge of the printed circuit board.
    Type: Application
    Filed: March 28, 2016
    Publication date: April 25, 2019
    Applicant: Intel IP Corporation
    Inventors: Sven Albers, Marc Dittes, Andreas Wolter, Klaus Reingruber, Georg Seidemann, Christian Geissler, Thomas Wagner, Richard Patten
  • Patent number: 10228725
    Abstract: A flexible band wearable electronic device includes a plurality of rigid links. The flexible band wearable electronic device also includes a number of pivot joints coupling the plurality of rigid links together. The flexible band wearable electronic device further includes a first electronic device on a first of the plurality of rigid links, and a second electronic device on a second of the plurality of rigid links. The flexible band wearable electronic device still further includes an electrical communication pathway between first electronic device and the second electronic device and through at least a portion of one of the number of pivot joints.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: March 12, 2019
    Assignee: Intel IP Corporation
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Thorsten Meyer, Gerald Ofner
  • Publication number: 20190072732
    Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
    Type: Application
    Filed: November 6, 2018
    Publication date: March 7, 2019
    Applicant: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
  • Patent number: 10209466
    Abstract: Disclosed is a package comprising a substrate having a patterned surface with an optical contact area, an optical redistribution layer (oRDL) feature, and a build-up material extending over the patterned surface of the substrate and around portions of the oRDL features. In some embodiments, the package comprises a liner sheathing the oRDL features. In some embodiments, the oRDL feature extends through openings in an outer surface of the build-up material and forms posts extending outward from the outer surface. In some embodiments, the package comprises an electrical redistribution layer (eRDL) feature, at least some portion of which overlap at least some portion of the oRDL feature. In some embodiments, the package comprises an optical fiber coupled to the oRDL features.
    Type: Grant
    Filed: April 2, 2016
    Date of Patent: February 19, 2019
    Assignee: Intel IP Corporation
    Inventors: Georg Seidemann, Christian Geissler, Sven Albers, Thomas Wagner, Marc Dittes, Klaus Reingruber, Andreas Wolter, Richard Patten
  • Publication number: 20190043800
    Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.
    Type: Application
    Filed: October 4, 2018
    Publication date: February 7, 2019
    Inventors: Klaus Jürgen REINGRUBER, Sven ALBERS, Christian Georg GEISSLER, Georg SEIDEMANN, Bernd WAIDHAS, Thomas WAGNER, Marc DITTES
  • Publication number: 20180374819
    Abstract: A method includes aligning a wire with a package body having a contact pad and moving the wire through the package body to form electrical contact with the contact pad.
    Type: Application
    Filed: December 18, 2015
    Publication date: December 27, 2018
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Publication number: 20180358317
    Abstract: An apparatus is described that includes a redistribution layer and a semiconductor die on the redistribution layer. An electrically conductive layer resides over the semiconductor die. A compound mold resides over the electrically conductive layer.
    Type: Application
    Filed: December 23, 2015
    Publication date: December 13, 2018
    Inventors: Sven ALBERS, Klaus REINGRUBER, Georg SEIDEMANN, Christian GEISSLER, Richard PATTEN
  • Publication number: 20180331070
    Abstract: Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.
    Type: Application
    Filed: December 26, 2015
    Publication date: November 15, 2018
    Applicant: Intel IP Corporation
    Inventors: Georg SEIDEMANN, Klaus REINGRUBER, Christian GEISSLER, Sven ALBERS, Andreas WOLTER, Marc DITTES, Richard PATTEN
  • Publication number: 20180331080
    Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Inventors: Christian Geissler, Sven Albers, Georg Seidemann, Andreas Wolter, Klaus Reingruber, Thomas Wagner, Marc Dittes
  • Publication number: 20180331053
    Abstract: An electrical device includes a redistribution layer structure, an inter-diffusing material contact structure and a vertical electrically conductive structure located between the redistribution layer structure and the inter-diffusing material contact structure. The vertical electrically conductive structure includes a diffusion barrier structure located adjacently to the inter-diffusing material contact structure. Further, the diffusion barrier structure and the redistribution layer structure comprise different lateral dimensions.
    Type: Application
    Filed: December 21, 2015
    Publication date: November 15, 2018
    Inventors: Christian GEISSLER, Sven ALBERS, Georg SEIDEMANN, Andreas WOLTER, Klaus REINGRUBER, Thomas WAGNER, Marc DITTES
  • Patent number: 10128205
    Abstract: Embodiments of the present disclosure describe integrated circuit (IC) package assemblies and methods of fabricating IC package assemblies. These embodiments include dies embedded in embedding substrates to provide larger pitch interconnects to facilitate coupling to substrates or circuit boards through flip chip techniques. The embedding substrates may contain conductive pathways for coupling die contacts to larger pitch contacts located on the embedding substrate. By embedding the dies in the embedding substrates, dies having smaller pitch contacts can be used in package assemblies with larger pitch components without the need for silicon interposers and without having to utilize more stringent pick and place operations. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 6, 2014
    Date of Patent: November 13, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Sven Albers
  • Patent number: 10121726
    Abstract: Embodiments of the present disclosure relate to a cooler for semiconductor devices. The semiconductor device may be electrically coupleable to a power source. The device may generate heat when the power source supplies power to the device during use of the device. The cooler may be coupled to one or more surfaces of the device. The cooler may include a hydrophilic material to adsorb water from ambient air. During operation of the device, the cooler may cool the device by conduction of heat away from the device to the cooler. The cooler may include water that is evaporated during use of the device to increase cooling capacity of the cooler. The cooler may be recharged with water from humidity in air when the device is not operated or operated at a lower power level. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 6, 2018
    Assignee: INTEL IP CORPORATION
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter, Georg Seidemann, Christian Geissler, Alexandra Atzesdorfer, Sonja Koller
  • Patent number: 10115668
    Abstract: Semiconductor packages having variable redistribution layer thicknesses are described. In an example, a semiconductor package includes a redistribution layer on a dielectric layer, and the redistribution layer includes first conductive traces having a first thickness and second conductive traces having a second thickness. The first thickness may be different than the second thickness, e.g., the first thickness may be less than the second thickness.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 30, 2018
    Assignee: Intel IP Corporation
    Inventors: Klaus Jürgen Reingruber, Sven Albers, Christian Georg Geissler, Georg Seidemann, Bernd Waidhas, Thomas Wagner, Marc Dittes
  • Publication number: 20180286799
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Application
    Filed: June 4, 2018
    Publication date: October 4, 2018
    Inventors: Thorsten MEYER, Gerald OFNER, Andreas WOLTER, Georg SEIDEMANN, Sven ALBERS, Christian GEISSLER
  • Publication number: 20180226185
    Abstract: An electronic package that includes a substrate; a first electronic component mounted on one side of the substrate; a second electronic component mounted on an opposing side of the substrate; a core mounted to the substrate, wherein the core extends through the substrate; a first wire electrically attached to at least one of the first electronic component and the substrate, wherein the first wire is wrapped around the core to form a first coil on the one side of the substrate; and a second wire electrically attached to at least one of the second electronic component and the substrate, wherein the second wire is wrapped around the core to form a second coil on the opposing side of the substrate.
    Type: Application
    Filed: January 4, 2018
    Publication date: August 9, 2018
    Inventors: Sven Albers, Klaus Reingruber, Andreas Wolter
  • Patent number: 9997444
    Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: June 12, 2018
    Assignee: Intel Corporation
    Inventors: Thorsten Meyer, Gerald Ofner, Andreas Wolter, Georg Seidemann, Sven Albers, Christian Geissler