Patents by Inventor Sven Van Elshocht

Sven Van Elshocht has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9997458
    Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: June 12, 2018
    Assignee: IMEC vzw
    Inventors: Laure Elisa Carbonell, Antony Premkumar Peter, Marc Schaekers, Sven Van Elshocht, Zsolt Tokei
  • Patent number: 9343298
    Abstract: The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack.
    Type: Grant
    Filed: September 26, 2011
    Date of Patent: May 17, 2016
    Assignee: IMEC
    Inventors: Mihaela Ioana Popovici, Johan Swerts, Malgorzata Pawlak, Kazuyuki Tomida, Min-Soo Kim, Jorge Kittl, Sven Van Elshocht
  • Publication number: 20150130062
    Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.
    Type: Application
    Filed: May 14, 2013
    Publication date: May 14, 2015
    Applicant: IMEC VZW
    Inventors: Laure Elisa Carbonell, Antony Premkumar Peter, Marc Schaekers, Sven Van Elshocht, Zsolt Tokei
  • Patent number: 8921228
    Abstract: A method for forming a noble metal layer by Plasma Enhanced Atomic Layer Deposition (PE-ALD) is disclosed. The method includes providing a substrate in a PE-ALD chamber, the substrate comprising a first region having an exposed first material and a second region having an exposed second material. The first material comprises a metal nitride or a nitridable metal, and the second material comprises a non-nitridable metal or silicon oxide. The method further includes depositing selectively by PE-ALD a noble metal layer on the second region and not on the first region, by repeatedly performing a deposition cycle including (a) supplying a noble metal precursor to the PE-ALD chamber and contacting the noble metal precursor with the substrate in the presence of a carrier gas followed by purging the noble metal precursor, and (b) exposing the substrate to plasma while supplying ammonia and the carrier gas into the PE-ALD chamber.
    Type: Grant
    Filed: October 3, 2012
    Date of Patent: December 30, 2014
    Assignee: IMEC
    Inventors: Johan Swerts, Sven Van Elshocht, Annelies Delabie
  • Patent number: 8649154
    Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: February 11, 2014
    Assignee: IMEC
    Inventors: Mihaela Ioana Popovici, Johan Swerts, Jorge Kittl, Sven Van Elshocht
  • Patent number: 8441064
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: August 11, 2011
    Date of Patent: May 14, 2013
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8405166
    Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: March 26, 2013
    Assignee: IMEC
    Inventors: Christoph Adelmann, Johan Swerts, Sven Van Elshocht, Jorge Kittl
  • Publication number: 20120092807
    Abstract: The disclosure provides a method for producing a stack of layers on a semiconductor substrate. The method includes producing a substrate a first conductive layer; and producing by ALD a sub-stack of layers on said conductive layer, at least one of said layers of the sub-stack being a TiO2 layer, the other layers of the sub-stack being layers of a dielectric material having a composition suitable to form a cubic perovskite phase upon crystallization of said sub-stack of layers. Crystallization is obtained via heat treatment. When used in a metal-insulator-metal capacitor, the stack of layers can provide improved characteristics as a consequence of the TiO2 layer being present in the sub-stack.
    Type: Application
    Filed: September 26, 2011
    Publication date: April 19, 2012
    Applicant: IMEC
    Inventors: Mihaela Ioana Popovici, Johan Swerts, Malgorzata Pawlak, Kazuyuki Tomida, Min-Soo Kim, Jorge Kittl, Sven Van Elshocht
  • Publication number: 20120075767
    Abstract: Methods of manufacturing metal-insulator-metal capacitor structures, and the metal-insulator-metal capacitor structures obtained, are disclosed. In one embodiment, a method includes providing a substrate, forming on the substrate a first metal layer comprising a first metal, and using atomic layer deposition with an H2O oxidant to deposit on the first metal layer a protective layer comprising TiO2. The method further includes using atomic layer deposition with an O3 oxidant to deposit on the protective layer a dielectric layer of a dielectric material, and forming on the dielectric layer a second metal layer comprising a second metal. In another embodiment, a metal-insulator-metal capacitor includes a bottom electrode comprising a first metal, a protective layer deposited on the bottom electrode and comprising TiO2, a dielectric layer deposited on the protective layer and comprising a dielectric material, and a top electrode formed on the dielectric layer and comprising a second metal.
    Type: Application
    Filed: September 28, 2011
    Publication date: March 29, 2012
    Applicant: IMEC
    Inventors: Mihaela Ioana Popovici, Johan Swerts, Jorge Kittl, Sven Van Elshocht
  • Publication number: 20110291179
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Application
    Filed: August 11, 2011
    Publication date: December 1, 2011
    Applicant: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Patent number: 8021948
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: September 20, 2011
    Assignee: IMEC
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Publication number: 20110147900
    Abstract: The present disclosure is related to a dielectric layer comprising a rare-earth aluminate (RExAl2-xO3 with 0<x<2) and having a perovskite crystalline structure, wherein the rare-earth aluminate comprises a rare-earth element having an atomic number higher than or equal to 63 and lower than or equal to 71. The disclosure also relates to method of manufacturing of a dielectric stack and a dielectric stack comprising said rare-earth aluminate dielectric layer and further comprising a template stack comprising at least an upper template layer, wherein the upper template layer has a perovskite structure, and wherein the upper template layer is underlying and in contact with the rare-earth aluminate dielectric layer. In a preferred embodiment the dielectric stack further comprises a lower template layer having a crystalline structure, wherein the lower template layer is underlying and in contact with the upper template layer.
    Type: Application
    Filed: December 7, 2010
    Publication date: June 23, 2011
    Applicant: IMEC
    Inventors: Christoph Adelmann, Johan Swerts, Sven Van Elshocht, Jorge Kittl
  • Publication number: 20090166715
    Abstract: A method for manufacturing a non-volatile memory device is described. The method comprises growing a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored. A non-volatile memory device is also described. In the non-volatile memory device, the interpoly/blocking dielectric comprises a layer in a siliconoxide consuming material, e.g. DyScO, on top of the upper layer of the layer where charge is stored, the siliconoxide consuming material having consumed at least part of the upper layer.
    Type: Application
    Filed: December 18, 2008
    Publication date: July 2, 2009
    Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)
    Inventors: Bogdan Govoreanu, Stefan De Gendt, Sven Van Elshocht, Tom Schram
  • Publication number: 20080308881
    Abstract: The present disclosure relates to methods for forming a gate stack in a MOSFET device and to MOSFET devices obtainable through such methods. In exemplary methods described herein, a rare-earth-containing layer is deposited on a layer of a silicon-containing dielectric material. Before these layers are annealed, a gate electrode material is deposited on the rare-earth-containing layer. Annealing is performed after the deposition of the gate electrode material, such that a rare earth silicate layer is formed.
    Type: Application
    Filed: January 10, 2008
    Publication date: December 18, 2008
    Applicants: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC), TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Stefan De Gendt, Lars-Ake Ragnarsson, Sven Van Elshocht, Shih-Hsun Chang, Christoph Adelmann, Tom Schram