Abstract: A pad structure includes an insulating layer; a first metal layer formed on one surface of the insulating layer and including an intermetallic compound layer of copper and tin or a tin layer; and a second metal layer formed on the first metal layer and including a gold layer.

Abstract: A semiconductor device includes a semiconductor substrate. The semiconductor substrate includes a first surface, a second surface, and a through hole that extends through the semiconductor substrate from the first surface to the second surface. An insulating layer covers the first surface and includes an opening at a location facing the through hole. An insulating film covers an inner wall of the through hole and an inner wall of the opening. A through electrode is formed in the through hole and the opening that are covered by the insulating film. A first connecting terminal is formed integrally with the through electrode to cover one end of the through electrode exposed from the insulating layer. The first connecting terminal has a larger size than the through electrode as viewed from above.

Abstract: A pad structure includes an insulating layer; a first metal layer formed on one surface of the insulating layer and including an intermetallic compound layer of copper and tin or a tin layer; and a second metal layer formed on the first metal layer and including a gold layer.

Abstract: Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member.

Abstract: A semiconductor device includes a supporting board having a protection film thereon; a semiconductor chip provided on the supporting board; a first internal connecting terminal formed on the supporting board; a second internal connecting terminal formed on the semiconductor chip; a first insulation layer for covering an upper surface of the supporting board and upper and lateral surfaces of the semiconductor chip; a wiring pattern provided on the first insulation layer, the wiring pattern connecting the first and second internal connecting terminals; a solder resist layer provided on the first insulation layer and the wiring pattern, the solder resist layer having an opening part; an external connecting terminal provided so as to connect to the wiring pattern through the opening part; a groove part formed on outer peripheries of the supporting board, the protection film, and the first insulation layer; and a resin layer formed in the groove part.

Abstract: A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal.

Abstract: A method include disposing a semiconductor chip having an electrode pad formed on a circuit forming surface on one surface of a support so that the electrode pad contacts with the one surface of the support, forming a first insulating layer on the one surface of the support so that the first insulating layer covers at least a side surface of the semiconductor chip, removing the support and forming an interconnection terminal on the electrode pad, forming a second insulating layer on the circuit forming surface of the semiconductor chip and the first insulating layer so that the second insulating layer covers the interconnection terminal, exposing an end portion of the interconnection terminal from a top surface of the second insulating layer, and forming a wiring pattern that is electrically connected to the end portion of the interconnection terminal, on the top surface of the second insulating layer.

Abstract: An electronic component mounting package includes a structure (coreless substrate) in which a plurality of wiring layers are stacked one on top of another with insulating layers interposed therebetween and are interconnected through via holes formed in the insulating layers. The entire surface of the coreless substrate, exclusive of pad portions defined at desired positions of the outermost wiring layers thereof, is covered with a molding resin. Further, an interposer is mounted on the side of the electronic component mounting surface of the coreless substrate, and the molding resin is partially filled into a gap between the coreless substrate and the interposer.

Abstract: Semiconductor chips are placed in recesses of a support carrier with electrode surfaces facing upward in a state where the semiconductor chips are arranged separately from each other. A seal resin part is formed by encapsulating the semiconductor chips by an insulating resin on said support carrier. Rewiring patterns are formed on a top surface of the seal resin part. External connection terminals are formed on the rewiring patterns. Bottom parts of the recesses of the support carrier are removed from the seal resin part while maintaining reinforcing members of the support carrier to be remained. The semiconductor packages are individualized by cutting the seal resin part along an outside of each reinforcing member.

Abstract: A semiconductor device includes a supporting board having a protection film thereon; a semiconductor chip provided on the supporting board; a first internal connecting terminal formed on the supporting board; a second internal connecting terminal formed on the semiconductor chip; a first insulation layer for covering an upper surface of the supporting board and upper and lateral surfaces of the semiconductor chip; a wiring pattern provided on the first insulation layer, the wiring pattern connecting the first and second internal connecting terminals; a solder resist layer provided on the first insulation layer and the wiring pattern, the solder resist layer having an opening part; an external connecting terminal provided so as to connect to the wiring pattern through the opening part; a groove part formed on outer peripheries of the supporting board, the protection film, and the first insulation layer; and a resin layer formed in the groove part.

Abstract: A manufacturing method of a semiconductor device, including a first step of forming a first electrode pad at an external edge part of a semiconductor chip mounting area of a supporting board; a second step of fixing a rear surface of a semiconductor chip having a main surface, the main surface where a second electrode pad is formed, to an inside of an area of the main surface of the supporting board, the area where the first electrode pad is formed; a third step of forming a first internal connecting terminal on the first electrode pad, and forming a second internal connecting terminal on the second electrode pad; and a fourth step of forming a first insulation layer on the main surface of the supporting board.

Abstract: A manufacturing method of a semiconductor device, including a first step of forming a first electrode pad at an external edge part of a semiconductor chip mounting area of a supporting board; a second step of fixing a rear surface of a semiconductor chip having a main surface, the main surface where a second electrode pad is formed, to an inside of an area of the main surface of the supporting board, the area where the first electrode pad is formed; a third step of forming a first internal connecting terminal on the first electrode pad, and forming a second internal connecting terminal on the second electrode pad; and a fourth step of forming a first insulation layer on the main surface of the supporting board.

Abstract: A disclosed semiconductor device includes a semiconductor chip having an electrode pad on a circuit forming face of the semiconductor chip, an internal connection terminal formed on the electrode pad, a stepped portion formed along an outer edge portion of the circuit forming face of the semiconductor chip, a first insulating layer formed on the circuit forming face of the semiconductor chip to cover at least the stepped portion, a second insulating layer formed on the circuit forming face of the semiconductor chip to cover the first insulating layer, and an interconnection formed on the second insulating layer and electrically connected to the electrode pad via the internal connection terminal.

Abstract: An electronic component mounting package includes a structure (coreless substrate) in which a plurality of wiring layers are stacked one on top of another with insulating layers interposed therebetween and are interconnected through via holes formed in the insulating layers. The entire surface of the coreless substrate, exclusive of pad portions defined at desired positions of the outermost wiring layers thereof, is covered with a molding resin. Further, an interposer is mounted on the side of the electronic component mounting surface of the coreless substrate, and the molding resin is partially filled into a gap between the coreless substrate and the interposer.