Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: It is an object of the present invention to provide a technology of a semiconductor integrated circuitry that allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operated faster. In a method for manufacturing such a semiconductor integrated circuitry of the present invention, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes is formed the first side wall spacer 14 composed of silicon nitride and the second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and are formed connecting portion connecting a conductor 20 to a bit line BL.

Abstract: A technology for a semiconductor integrated circuitry allows each of the DRAM memory cells to be divided finely so as to be more highly integrated and operate faster. In a method of manufacturing such a semiconductor integrated circuit, at first, gate electrodes 7 are formed via a gate insulating film 6 on the main surface of a semiconductor substrate 1, and on side surfaces of each of the gate electrodes there is formed a first side wall spacer 14 composed of silicon nitride and a second side wall spacer 15 composed of silicon oxide. Then, in the selecting MISFET Qs in the DRAM memory cell area there are opened connecting holes 19 and 21 in a self-matching manner with respect to the first side wall spacers 14 and connecting portion is formed connecting a conductor 20 to a bit line BL.

Abstract: A connector for forming a series electrical connection between opposing ends of a pair of insulation-covered wires comprises a lower body portion having a longitudinal groove and a pair of upper body portions connected to and superimposable upon the lower body portion. Each of the upper body portions has a longitudinal groove for receiving and maintaining one wire end within the groove in the lower body portion. Each of the upper and lower body portions contain formations for receiving a conductive connecting piece having a pair of opposed blade portions for piercing the insulation to contact each wire end for forming a series connection. Opposing ends of the groove in the lower body portion and the outer ends of the groove in each upper body portion are formed with a thin yieldable wall for resiliently holding each wire end.

Abstract: An electrical parallel connector comprising an integral unitary structure formed of electrical insulation hard synthetic resin and including a rectangular first connector member and a rectangular second connector member integrally connected to said first connector member by means of flexible connection strips, said first connector member having a plurality of parallel grooves extending by a substantial portion of the length of the connector member in one major surface thereof and terminating short of the opposite ends of the connector member to provide end walls which define the opposite ends of said grooves, projections on the opposite sides of said connector member for engaging the opposite sides of the second connector member, recesses in the opposite side edges of said connector member positioned adjacent to and inwardly of said projections and extending into the bottom of the adjacent groove at right angles to the groove and an intermediate recess positioned between said first mentioned recesses and exte