Patents by Inventor Syuuichi Kariyazaki

Syuuichi Kariyazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8680691
    Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: March 25, 2014
    Assignee: Renesas Electronics Corporation
    Inventor: Syuuichi Kariyazaki
  • Publication number: 20120068362
    Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
    Type: Application
    Filed: November 28, 2011
    Publication date: March 22, 2012
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventor: Syuuichi KARIYAZAKI
  • Publication number: 20100176504
    Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
    Type: Application
    Filed: March 24, 2010
    Publication date: July 15, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Syuuichi Kariyazaki
  • Patent number: 6723627
    Abstract: There is provided a method for manufacturing semiconductor devices includes the steps of: packaging onto a wiring board a semiconductor chip that flux is coated to its right face onto which ball-like solder electrodes are connected; forcedly spraying a washing solution to an under-fill portion between the semiconductor chip and the wiring board, to wash off the flux; and exposing the wiring board to an oxygen-plasma atmosphere to conduct plasma processing on the wiring board.
    Type: Grant
    Filed: October 3, 2000
    Date of Patent: April 20, 2004
    Assignee: NEC Corporation
    Inventors: Syuuichi Kariyazaki, Hirokazu Honda
  • Publication number: 20030161124
    Abstract: In a wiring-design system for designing a wiring-arrangement for a wiring-board on which an area-input/output type semiconductor chip is mounted, a display unit displays a lattice representing an array of pads to be provided on a chip surface of the semiconductor chip. A first layout design system defines and arranges various IO blocks on the lattice to thereby design a first layout of IO blocks thereon. A check system checks whether or not the first layout of IO blocks is properly performed in accordance with a layout rule. When the check system confirms that the first layout of IO blocks is properly performed, a second layout design system designs a second layout of IO block to be provided on the wiring-board, based on the first layout of IO blocks on the lattice. A wiring-arrangement is designed in the wiring-board concerning the second layout of IO blocks.
    Type: Application
    Filed: February 25, 2003
    Publication date: August 28, 2003
    Applicant: NEC Electronics Corporation
    Inventor: Syuuichi Kariyazaki
  • Publication number: 20010050423
    Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 13, 2001
    Applicant: NEC Corporation
    Inventor: Syuuichi Kariyazaki