Patents by Inventor Szuya Liao

Szuya Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105725
    Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor and a second transistor stacked vertically. A conductive via extends vertically from a first source/drain region of the first transistor past the second transistor. The second transistor includes an asymmetric second source/drain region. The asymmetry of the second source/drain region helps ensure that the second source/drain region does not contact the conductive via.
    Type: Application
    Filed: March 30, 2023
    Publication date: March 28, 2024
    Inventors: Gerben Doornbos, Marcus Johannes Henricus Van Dal, Szuya Liao, Chung-Te Lin
  • Publication number: 20240072115
    Abstract: A device includes: a complementary transistor including: a first transistor having a first source/drain region and a second source/drain region; and a second transistor stacked on the first transistor, and having a third source/drain region and a fourth source/drain region, the third source/drain region overlapping the first source/drain region, the fourth source/drain region overlapping the second source/drain region. The device further includes: a first source/drain contact electrically coupled to the third source/drain region; a second source/drain contact electrically coupled to the second source/drain region; a gate isolation structure adjacent the first and second transistors; and an interconnect structure electrically coupled to the first source/drain contact and the second source/drain contact.
    Type: Application
    Filed: February 13, 2023
    Publication date: February 29, 2024
    Inventors: Wei-Xiang You, Wei-De Ho, Hsin Yang Hung, Meng-Yu Lin, Hsiang-Hung Huang, Chun-Fu Cheng, Kuan-Kan Hu, Szu-Hua Chen, Ting-Yun Wu, Wei-Cheng Tzeng, Wei-Cheng Lin, Cheng-Yin Wang, Jui-Chien Huang, Szuya Liao
  • Publication number: 20240047523
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack over a substrate. The method includes forming a spacer over first sidewalls of the gate stack using a first precursor. The first precursor includes a first boron- and nitrogen-containing material having a first hexagonal ring structure, the spacer has a plurality of first layers, and each first layer includes boron and nitrogen.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Ming LIN, Szu-Hua CHEN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240038595
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Jhih-Rong HUANG, Yi-Bo LIAO, Shuen-Shin LIANG, Min-Chiang CHUANG, Sung-Li WANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240030281
    Abstract: A semiconductor device having a low-k isolation structure and a method for forming the same are provided. The semiconductor device includes channel structures, laterally extending on a substrate; gate structures, intersecting and covering the channel structures; and a channel isolation structure, laterally penetrating through at least one of the channel structures, and extending between separate sections of one of the gate structures along an extending direction of the one of the gate structures. A low-k dielectric material in the channel isolation structure comprises boron nitride.
    Type: Application
    Filed: July 21, 2022
    Publication date: January 25, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hua Chen, Cheng-Ming Lin, Han-Yu Lin, Wei-Yen Woon, Ming-Jie Huang, Ting-Gang Chen, Tai-Chun Huang, Ming-Chang Wen, Szuya Liao
  • Publication number: 20240014042
    Abstract: A semiconductor device includes a fin, first source/drain regions, second source/drain regions, a first nanosheet, a second nanosheet and a metal gate structure. The fin extends in a first direction and protrudes above an insulator. The first source/drain regions are over the fin. The second source/drain regions are over the first source/drain regions. The first nanosheet extends in the first direction between the first source/drain regions. The second nanosheet extends in the first direction between the second source/drain regions. The metal gate structure is over the fin and between the first source/drain regions. The metal gate structure extends in a second direction different from the first direction from a first sidewall to a second sidewall. A first distance in the second direction between the first nanosheet and the first sidewall is smaller than a second distance in the second direction between the first nanosheet and the second sidewall.
    Type: Application
    Filed: July 10, 2022
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Yu Lin, Chun-Fu Cheng, Cheng-Yin Wang, Yi-Bo Liao, Szuya Liao
  • Publication number: 20240014282
    Abstract: A method is provided that includes depositing a catalyst layer along a surface of the opening and performing a selectivity enhancement process. The selectivity enhancement process alters a deposition rate of a metal component on at least one region of the catalyst layer. The metal component is deposited on the catalyst layer. Exemplary selectivity enhancement processes include a self-assembled monolayer (SAM), introducing an accelerator, and/or introducing a suppressor.
    Type: Application
    Filed: January 26, 2023
    Publication date: January 11, 2024
    Inventors: Kuan-Kan HU, Tsung-Kai CHIU, Wei-Yen WOON, Szuya LIAO, Ku-Feng YANG
  • Publication number: 20230411211
    Abstract: Provided are an interconnect structure and a method of forming the same. The method includes: forming an opening in a dielectric layer; forming a 2D material layer to conformally cover a surface of the opening; performing a nitridation treatment on the 2D material layer to form a nitrided 2D material layer; forming a metal layer on the nitrided 2D material layer and filling in the opening; and performing a planarization process on the metal layer and the nitrided 2D material layer to expose a top surface of the dielectric layer.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yang Li, Chih-Piao Chuu, Szuya Liao, Han Wang
  • Publication number: 20230402386
    Abstract: A semiconductor device includes a substrate and an interconnection layer disposed on the substrate. The interconnection layer includes a plurality of etch-stop layers, a plurality of first dielectric layers, and a plurality of conductive layers. The first dielectric layers are disposed on the plurality of etch-stop layers, wherein the plurality of first dielectric layers comprises porous organic framework (POF) dielectrics having a dielectric constant of 2 or less, and a thermal conductivity of 1 W/(m·K) or more. The conductive layers are embedded in the first dielectric layers.
    Type: Application
    Filed: June 13, 2022
    Publication date: December 14, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Hua Chen, Wei-Yen Woon, Szuya Liao
  • Publication number: 20230402528
    Abstract: Semiconductor structures and methods of forming the same are provided. In an embodiment, an exemplary method includes forming a dummy gate stack engaging a semiconductor fin over a substrate, conformally depositing a first dielectric layer over the substrate, conformally depositing a second dielectric layer over the first dielectric layer, etching back the first dielectric layer and the second dielectric layer to form a gate spacer extending along a sidewall surface of the dummy gate stack, the gate spacer comprising the first dielectric layer and the second dielectric layer, forming source/drain features in and over the semiconductor fin and adjacent the dummy gate stack, and replacing the dummy gate stack with a gate structure, where a dielectric constant of the first dielectric layer is less than a dielectric constant of silicon oxide, and the second dielectric layer is less easily to be oxidized than the first dielectric layer.
    Type: Application
    Filed: March 2, 2023
    Publication date: December 14, 2023
    Inventors: Szu-Hua Chen, Cheng-Ming Lin, Wei-Xiang You, Wei-De Ho, Wei-Yen Woon, Szuya Liao
  • Publication number: 20230345693
    Abstract: An integrated circuit includes a plurality of SRAM cells. Each SRAM cell includes a first inverter having a first N-type transistor and a first P-type transistor stacked vertically in a first active region. The SRAM cell includes a second inverter cross-coupled with the first inverter and including a second N-type transistor and a second P-type transistor stacked vertically in a second active region. The SRAM cell includes a butt contact electrically connecting an output of the first inverter to an input of the second inverter. The butt contact is at least partially within a first active region.
    Type: Application
    Filed: February 2, 2023
    Publication date: October 26, 2023
    Inventors: Cheng-Yin WANG, Szuya Liao, Jui-Chien Huang
  • Publication number: 20230317674
    Abstract: Semiconductor devices and methods are provided which facilitate improved thermal conductivity using a high-kappa dielectric bonding layer. In at least one example, a device is provided that includes a first substrate. A semiconductor device layer is disposed on the first substrate, and the semiconductor device layer includes one or more semiconductor devices. Frontside interconnect structure are disposed on the semiconductor device layer, and a bonding layer is disposed on the frontside interconnect structure. A second substrate is disposed on the bonding layer. The bonding layer has a thermal conductivity greater than 10 W/m·K.
    Type: Application
    Filed: January 6, 2023
    Publication date: October 5, 2023
    Inventors: Che Chi SHIH, Cheng-Ting CHUNG, Han-Yu LIN, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20230307285
    Abstract: A semiconductor device with isolation structures and a method of fabricating the same are disclosed. The semiconductor device includes first and second FETs, an isolation structure, and a conductive structure. The first FET includes a first fin structure, a first array of gate structures disposed on the first fin structure, and a first array of S/D regions disposed on the first fin structure. The second FET includes a second fin structure, a second array of gate structures disposed on the second fin structure, and a second array of S/D regions disposed on the second fin structure. The isolation structure includes a fill portion and a liner portion disposed between the first and second FETs and in physical contact with the first and second arrays of gate structures. The conductive structure is disposed in the liner portion and conductively coupled to a S/D region of the second array of S/D regions.
    Type: Application
    Filed: August 19, 2022
    Publication date: September 28, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Chien Huang, Sandy Szuya Liao, Cheng-Yin Wang, Wei-Cheng Lin, Wei-Chen Tzeng
  • Publication number: 20230307456
    Abstract: An integrated circuit includes a complimentary field effect transistor (CFET). The CFET includes a first transistor having a first semiconductor nanostructure corresponding to a channel region of the first semiconductor nanostructure and a first gate metal surrounding the second semiconductor nanostructure. The CFET includes a transistor including a second semiconductor nanostructure above the first semiconductor nanostructure and a second gate metal surrounding the second semiconductor nanostructure. The CFET includes an isolation structure between the first and second semiconductor nanostructures.
    Type: Application
    Filed: August 15, 2022
    Publication date: September 28, 2023
    Inventors: Meng-Yu LIN, Yi-Han WANG, Chun-Fu CHENG, Cheng-Yin WANG, Yi-Bo LIAO, Szuya LIAO
  • Publication number: 20230178435
    Abstract: A method includes forming a first transistor of a first semiconductor device. The first semiconductor device includes a first channel region and a gate electrode on the first channel region. A second semiconductor device is bonded to the first semiconductor device by a bonding layer disposed between the first and second semiconductor devices. A second transistor of the second semiconductor device is formed that includes a second channel region and a second gate electrode on the second channel region. The bonding layer is disposed between the first gate electrode of the first transistor and the second gate electrode of the second transistor.
    Type: Application
    Filed: July 8, 2022
    Publication date: June 8, 2023
    Inventors: Jui-Chien HUANG, Szuya LIAO, Cheng-Yin WANG, Shih Hao WANG
  • Publication number: 20230008517
    Abstract: A transistor includes a gate structure, a channel layer underlying the gate structure and comprising a two-dimensional (2D) material, source/drain contacts laterally spaced apart from the gate structure and disposed laterally next to the channel layer, and a spacer laterally interposed between the gate structure and the source/drain contacts. A semiconductor device and a semiconductor structure are also provided.
    Type: Application
    Filed: January 13, 2022
    Publication date: January 12, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Ching Cheng, Jui-Chien Huang, Yi-Tse Hung, Shih Hao Wang, Han Wang, Szuya Liao