Patents by Inventor Ta-Sheng Lin

Ta-Sheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240120337
    Abstract: A semiconductor device structure includes a first dielectric wall, a plurality of first semiconductor layers vertically stacked and extending outwardly from a first side of the first dielectric wall, each first semiconductor layer has a first width, a plurality of second semiconductor layers vertically stacked and extending outwardly from a second side of the first dielectric wall, each second semiconductor layer has a second width, a plurality of third semiconductor layers disposed adjacent the second side of the first dielectric wall, each third semiconductor layer has a third width greater than the second width, a first gate electrode layer surrounding at least three surfaces of each of the first semiconductor layers, the first gate electrode layer having a first conductivity type, and a second gate electrode layer surrounding at least three surfaces of each of the second semiconductor layers, the second gate electrode layer having a second conductivity type opposite the first conductivity type.
    Type: Application
    Filed: January 15, 2023
    Publication date: April 11, 2024
    Inventors: Ta-Chun LIN, Chih-Hung HSIEH, Chun-Sheng LIANG, Wen-Chiang HONG, Chun-Wing YEUNG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240113165
    Abstract: A semiconductor device includes a substrate, a first stack of semiconductor nanosheets, a second stack of semiconductor nanosheets, a gate structure and a first dielectric wall. The substrate includes a first fin and a second fin. The first stack of semiconductor nanosheets is disposed on the first fin. The second stack of semiconductor nanosheets is disposed on the second fin. The gate structure wraps the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall is disposed between the first stack of semiconductor nanosheets and the second stack of semiconductor nanosheets. The first dielectric wall includes at least one neck portion between adjacent two semiconductor nanosheets of the first stack.
    Type: Application
    Filed: January 10, 2023
    Publication date: April 4, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng Liang, Chih-Hao Chang, Jhon Jhy Liaw
  • Publication number: 20240105805
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes channel structures vertically stacked over a substrate and a source/drain structure laterally attached to the channel structures in the first direction. The semiconductor structure also includes a dielectric wall structure laterally attached to the channel structures in the second direction. The second direction is different from the first direction. In addition, the dielectric wall structure includes a bottom portion and a cap layer formed over the bottom portion. The semiconductor structure also includes an isolation feature vertically overlapping the cap layer of the dielectric wall structure and a gate structure formed around the channel structures and covering a sidewall of the isolation feature.
    Type: Application
    Filed: February 2, 2023
    Publication date: March 28, 2024
    Inventors: Chun-Sheng LIANG, Hong-Chih CHEN, Ta-Chun LIN, Shih-Hsun CHANG, Chih-Hao CHANG
  • Publication number: 20240088149
    Abstract: A semiconductor structure includes: a substrate; a first fin and a second fin disposed on the substrate and spaced apart from each other; a dielectric wall disposed on the substrate and having first and second wall surfaces; a third fin disposed on the substrate to be in direct contact with at least one of the first and second fins; a first device disposed on the first fin and including first channel features extending away from the first wall surface; a second device disposed on the second fin and including second channel features extending away from the second wall surface; at least one third device disposed on the third fin and including third channel features; and an isolation feature disposed on the substrate to permit the third device to be electrically isolated from the first and second devices. A method for manufacturing the semiconductor structure is also disclosed.
    Type: Application
    Filed: February 15, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Ming-Heng TSAI, Huang-Chao CHANG, Chun-Sheng LIANG, Chih-Hao CHANG, Jhon Jhy LIAW
  • Publication number: 20240088278
    Abstract: A semiconductor structure includes spaced apart first and second fins over a substrate, a separating wall over the substrate and having opposite first and second wall surfaces, multiple first channel features extending away from the first wall surface over the first fin such that the first channel features are spaced apart, multiple second channel features extending away from the second wall surface over the second fin such that the second channel features are spaced apart, two spaced apart first epitaxial structures on the first fin such that each first channel feature interconnects the first epitaxial structures, two spaced apart second epitaxial structures on the second fin such that each second channel feature interconnects the second epitaxial structures, and a dielectric structure including at least one bottom dielectric portion separating at least one of the first and second epitaxial structures from a corresponding first and second fins.
    Type: Application
    Filed: January 12, 2023
    Publication date: March 14, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Chun-Wing YEUNG, Chih-Hao CHANG
  • Publication number: 20240079396
    Abstract: A package structure includes a first carrier, a second carrier, and a first electronic device. The first carrier is electrically connected to a first voltage. The second carrier includes a first substrate and a first interconnect structure. The first substrate is in contact with the first carrier, the first interconnect structure is electrically connected to a second voltage, and the first interconnect structure and the first carrier are deposited on two opposite sides of the first substrate. The first electronic device is deposited on the first interconnect structure and away from the first carrier. The first electronic device is in contact with the first interconnect structure.
    Type: Application
    Filed: November 30, 2022
    Publication date: March 7, 2024
    Inventors: Lung-Sheng LIN, Chih-Feng HUANG, Ta-Yung YANG
  • Publication number: 20240079447
    Abstract: Semiconductor structures and methods for manufacturing the same are provided. The semiconductor structure includes a first stack structure formed over a substrate, and the first stack structure includes a plurality of nanostructures that extend along a first direction. The semiconductor structure includes a second stack structure formed adjacent to the first stack structure, and the second stack structure includes a plurality of nanostructures that extend along the first direction. The semiconductor structure includes a first gate structure formed over the first stack structure, and the first gate structure extends along a second direction. The semiconductor structure also includes a dielectric wall between the first stack structure and the second stack structure, and the dielectric wall includes a low-k dielectric material, and the dielectric wall is connected to the first stack structure and the second stack structure.
    Type: Application
    Filed: February 3, 2023
    Publication date: March 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ta-Chun LIN, Chun-Sheng LIANG, Kuo-Hua PAN, Chih-Hao CHANG, Jhon-Jhy LIAW
  • Patent number: 11923413
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate. The semiconductor structure further includes a gate structure surrounding the nanostructures and a source/drain structure attached to the nanostructures. The semiconductor structure further includes a contact formed over the source/drain structure and extending into the source/drain structure.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ta-Chun Lin, Kuo-Hua Pan, Jhon-Jhy Liaw, Chao-Ching Cheng, Hung-Li Chiang, Shih-Syuan Huang, Tzu-Chiang Chen, I-Sheng Chen, Sai-Hooi Yeong
  • Publication number: 20230422112
    Abstract: According to an aspect of the disclosure, the disclosure is directed to a wireless communication apparatus on a vehicle. The wireless communication the apparatus includes (not limited to): first wireless transceiver configured to transmit and receive data on a first communication path; a second wireless transceiver configured to transmit and receive data on a second communication path; and a processor electrically connected to the first wireless transceiver and the second wireless transceiver and configured at least to: establish, as a default mean of communication, multiple communication paths; transmit by the first wireless transceiver, as the default mean of communication, a first data packet to the network located outside of the vehicle on a first communication path; and transmit by the second wireless transceiver, as the default mean of communication, a first duplicated data packet of the first data packet to the network on a second communication path.
    Type: Application
    Filed: January 9, 2023
    Publication date: December 28, 2023
    Applicant: Moxa Inc.
    Inventors: Ta-Sheng Lin, Jing-You Yan, Hung-Yu Wei
  • Publication number: 20040059821
    Abstract: Method and system for providing a PPP-Bridge operating mode in a data communication system is disclosed. Upon receiving a PPP connect request from a user terminal at the LAN interface in a dial-up mode of application, or through the use of pre-configuration in a leased-line mode of application, the access device establishes a PPP session with a remote PPP server via its WAN interface. Once the PPP session is established, the access device receives a public IP address from the remote PPP server and relays the received IP address via DHCP to the corresponding user terminal. To the data network, it appears as though the user terminal is operating with the public IP address from the remote PPP server, even though the PPP session is established between the access device and the remote PPP server. This method and system supports multiple PPP sessions through the use of user profiles stored on the access device.
    Type: Application
    Filed: September 24, 2002
    Publication date: March 25, 2004
    Inventors: Jian Tang, Ta-Sheng Lin, Xinzhang Ma, Guangjie Yang
  • Patent number: 5541911
    Abstract: Network traffic from a central device across a communication link to a remote device is controlled based upon central traffic management resources in the central device. The central traffic management resources are coupled to a communication link and monitor data packets received across the communication link to learn characteristics of the remote network. Based on the learned characteristics, traffic management messages are generated in the central traffic management resources. These messages are forwarded to an interface device on the remote network, where traffic on the communication link is controlled in response to the traffic management messages. Thus, the remote interface is configured automatically by central traffic management resources running in the central device without human intervention at the remote network. The traffic management messages manage traffic across a communication link of two types.
    Type: Grant
    Filed: October 12, 1994
    Date of Patent: July 30, 1996
    Assignee: 3Com Corporation
    Inventors: Chandrasekharan Nilakantan, Kiho Yum, Ta-Sheng Lin