Abstract: A resonant switching power converter circuit including: a switching converter, a control circuit and a pre-charging circuit; wherein the control circuit controls a first switch of the switching converter in a pre-charging mode, so as to control electrical connections between a first power and at least one of plural capacitors of the switching converter, and to control other switches of the switching converter, so as to control the pre-charging circuit to charge at least one capacitor to a predetermined voltage; wherein in a start-up mode, the plural switches control electrical connections of the capacitors according to first and second operation signals, such that after the pre-charging mode ends, the switching converter subsequently operates in the start-up mode; wherein in the start-up mode, the first and second operation signals have respective ON periods, and the time lengths of the ON periods increase gradually.

Abstract: A flyback converter includes a power transformer, a primary side switch, a secondary side switch and a controller. A secondary side switching signal has an SR pulse for achieving synchronous rectification, and a ZVS pulse for achieving zero voltage switching. The ZVS pulse is enabled according to a first characteristic of a resonance waveform, whereas, a primary side switching signal is enabled according to a second characteristic of resonance waveform. When an output current increases, the primary side switching signal is disabled during an inhibition interval, such that primary side switching signal does not overlap with the ZVS pulse, thereby preventing the primary and secondary side switches from being both conductive simultaneously. The inhibition interval is correlated with a rising edge of the primary side switching signal in a previous switching period and a resonance period of the resonance waveform.

Abstract: A DC-DC power conversion system includes a resonant switched-capacitor converter and a controller. The resonant switched-capacitor converter is switched between a first state and a second state to generate an output voltage, and includes an input terminal, a resonant tank, an output capacitor, a first set of switches and a second set of switches. The input terminal is used to receive an input voltage. The output capacitor is used to generate the output voltage. The first set of switches is turned on in the first state and turned off in the second state according to a first control signal. The second set of switches is turned on in the second state and turned off in the first state according to a second control signal. The controller adjusts the first control signal and the second control signal according to the output voltage.

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

Abstract: A spike suppression circuit includes a wide bandgap transistor, a first transistor, a clamping circuit, and a capacitor. The wide bandgap transistor is depletion-type. The first transistor is coupled in series with the wide bandgap transistor. The clamping circuit provides a voltage difference, and is coupled to a common node between the wide bandgap transistor and the first transistor. The capacitor provides a supply voltage for the clamping circuit. When the first transistor is turned off, the capacitor can recycle spike energy at the common node.

Abstract: A switched capacitor converter circuit includes: a conversion capacitor; an output capacitor; and switches configured to switch the coupling configurations of the conversion capacitor and the output capacitor according to a level of the first power supply voltage of the switched capacitor converter circuit, to generate the second power supply voltage at the output capacitor according to the first power supply voltage. The second power supply voltage provides power to control the power converter circuit. When the first power supply voltage is higher than a high threshold, the switched capacitor converter circuit controls the second power supply voltage to be lower than the first power supply voltage. When the first power supply voltage is lower than a low threshold, the switched capacitor converter circuit controls the second power supply voltage to be higher than the first power supply voltage.

Abstract: A switching regulator includes a first switch, a second switch, an inductor coupled to the first and second switches, and a control circuit. The control circuit controls the first switch to be ON for an ON time period. Next, the control circuit controls the first and second switches to be OFF for a first dead time period. Next, the control circuit controls the second switch to be ON for a synchronous rectification time period. Next, the control circuit controls the first and second switches to be OFF for a second dead time period. Next, the control circuit controls the second switch to be ON for a zero-voltage-switching pulse time period. Next, the control circuit controls the first and second switches to be OFF for a third dead time period. By the above operations, the first switch achieves soft switching.

Abstract: A flyback power converter circuit includes: a power transformer, a primary side switch and a conversion control circuit. In a DCM, during a dead time, the conversion control circuit calculates an upper limit frequency corresponding to output current according to a frequency upper limit function, and obtains a frequency upper limit masking period according to a reciprocal of the upper limit frequency, wherein the frequency upper limit masking period is a period starting from when the primary side switch is turned ON. During an upper limit selection period, the conversion control circuit selects a valley among one or more valleys in a ringing signal related to a voltage across the primary side switch as an upper limit locked valley, so that the conversion control circuit once again turns ON the primary side switch at a beginning time point of the upper limit locked valley.

Abstract: A multiple output universal serial bus travel adaptor includes: at least one AC-DC converter for converting an AC power to a first DC power; at least one DC-DC converter for providing a second DC power according to the first DC power; plural switches which are coupled to the AC-DC converter and/or the DC-DC converter to provide the first DC power or the second DC power to corresponding connectors according to operation signals; and a protocol controller configured to generate the operation signals according to at least one of the following parameters: a) the types of the connectors; b) whether there is a mobile device connected with the connectors; c) a first command from the mobile device; d) the power consumed by the mobile devices; e) the currents flowing through the connectors; and f) the voltages at the connectors.

Abstract: A flyback power converter includes: a first transistor switching a transformer for generating a primary switching current and an output voltage; and a second transistor generating a circulated current to achieve ZVS (zero voltage switching) of the first transistor; wherein the flyback power converter actively forces at least one switching cycle to be operated in a DCM (discontinuous conduction mode) operation when the primary switching current is determined to have been operating in a non-DCM operation for a predetermined number of switching cycles. The flyback power converter generates a demagnetized signal which emulates the demagnetized time of the transformer for controlling the second transistor during the non-DCM operation. The flyback power converter calibrates the demagnetized signal according to the demagnetized time during the actively fored DCM operation.

Abstract: A resonant half-bridge flyback power converter includes: a first transistor and a second transistor which form a half-bridge circuit; a transformer and a resonant capacitor connected in series and coupled to the half-bridge circuit; and a switching control circuit configured to generate a first driving signal and a second driving signal to control the first transistor and the second transistor respectively for switching the transformer to generate an output voltage. The first driving signal is configured to magnetize the transformer. The second driving signal includes at most one pulse between two consecutive pulses of the first driving signal. The switching control circuit generates a skipping cycle period when an output power is lower than a predetermined threshold. A resonant pulse of the second driving signal is skipped during the skipping cycle period. The skipping cycle period is increased in response to the decrease of the output power.

Abstract: A half-bridge flyback power converter: a first transistor, a second transistor and a third transistor which form a half-bridge circuit. The first transistor is turned on for generating a negative circulated current for achieving zero voltage switching of the second transistor. The second transistor is turned on for magnetizing a transformer. The third transistor is turned on during a demagnetized time period to generate an output voltage. The physical size of the first transistor is smaller than physical size of the third transistor.

Abstract: A resonant half-bridge flyback power converter includes: a power transformer and a resonant capacitor which are coupled in series between a half-bridge power stage and an output power; and a primary controller circuit controlling a high side power switch and a low side power switch of the half-bridge power stage. When the high side switch is OFF, the control signal of the low side power switch includes a resonant switching pulse for achieving resonant switching of the low side switch and a soft switching pulse for achieving ZVS of the high side switch. When the output power is lower than a delay threshold, the primary controller circuit determines a delay period which is between the resonant switching pulse and the soft switching pulse to control both the high side power switch and the low side power switch to be OFF. The delay period is negatively correlated with the output power.

Abstract: A two-stage power converter includes: a resonant switched-capacitor converter (RSCC) receiving an input voltage and generating a first stage voltage; a voltage regulator receiving the first stage voltage and generating an output voltage; and a communication interface and control circuit generating a charging operation signal, at least one discharging operation signal and a switching signal. The charging operation signal and the discharging operation signal are employed to control the RSCC to perform a charging process and at least one discharging process respectively, and the switching signal is employed to control the voltage regulator, so as to synchronize a resonant frequency of the RSCC and a switching frequency of the voltage regulator. The communication interface and control circuit adjusts a delay interval after the discharging process ends, and starts the charging process at an end time point of the delay interval.

Abstract: The present invention provides a Zener diode and a manufacturing method thereof. The Zener diode includes: a semiconductor layer, an N-type region, and a P-type region. The N-type region has N-type conductivity, wherein the N-type region is formed in the semiconductor layer beneath an upper surface of the semiconductor layer, and in contact with the upper surface. The P-type region has P-type conductivity, wherein the P-type region is formed in the semiconductor layer and is completely beneath the N-type region, and in contact with the N-type region. The N-type region overlays the entire P-type region. The N-type region has an N-type conductivity dopant concentration, wherein the N-type conductivity dopant concentration is higher than a P-type conductivity dopant concentration of the P-type region.

Abstract: A switching converter circuit, which switches one terminal of an inductor to different voltages, includes a high side MOSFET, a low side MOSFET, and a driver circuit which includes a high side driver, a low side driver, and a dead time control circuit. According to an output current, The dead time control circuit adaptively delays a low side driving signal to generate a high side enable signal for enabling the high side driver to generate a high side driving signal according to a pulse width modulation (PWM) signal; and/or adaptively delays the high side driving signal to generate a low side enable signal for enabling the low side driver to generate the low side driving signal according to the PWM signal, so as to adaptively control a dead time in which the high side MOSFET and the low side MOSFET are both not conductive.

Abstract: A switching converter circuit for switching one end of an inductor therein between plural voltages according to a pulse width modulation (PWM) signal to convert an input voltage to an output voltage. The switching converter circuit has a driver circuit including a high side driver, a low side driver, a high side sensor circuit, and a low side sensor circuit. The high side sensor circuit is configured to sense a gate-source voltage of a high side metal oxide semiconductor field effect transistor (MOSFET), to generate a low side enable signal for enabling the low side driver to switch a low side MOSFET according to the PWM signal. The low side sensor circuit is configured to sense a gate-source voltage of a low side MOSFET, to generate a high side enable signal for enabling the high side driver to switch a high side MOSFET according to the PWM signal.

Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.

Abstract: A high voltage device includes: a semiconductor layer, a well region, a shallow trench isolation region, a drift oxide region, a body region, a gate, a source, and a drain. The drift oxide region is located on a drift region. The shallow trench isolation region is located below the drift oxide region. A part of the drift oxide region is located vertically above a part of the shallow trench isolation region and is in contact with the shallow trench isolation region. The shallow trench isolation region is formed between the drain and the body region.

Abstract: A switch capable of decreasing parasitic inductance includes: a semiconductor device, a first top metal line, and a second top metal line. The second top metal line electrically connects a power supply input end and a current inflow end of the semiconductor device, wherein a first part of the first top metal line is arranged in parallel and adjacent to a second part of the second top metal line. When the semiconductor device is in an ON operation, an input current outflows from the power supply input end, and is divided into a first current and a second current. When the first current and the second current flow through the first part and the second part respectively, the first current and the second current flow opposite to each other, to reduce an total parasitic inductance of the first top metal line and the second top metal line.