Patents by Inventor Tadaaki Bandoh
Tadaaki Bandoh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7111187Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: GrantFiled: November 6, 2003Date of Patent: September 19, 2006Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Publication number: 20040093532Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1 and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: ApplicationFiled: November 6, 2003Publication date: May 13, 2004Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
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Patent number: 6675311Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1, And the operation timing of an interface provided between at least one pair oflogic devices is synchronously controlled by the clock signal K1.Type: GrantFiled: December 6, 2001Date of Patent: January 6, 2004Assignee: HItachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Publication number: 20020059538Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K1. and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K1.Type: ApplicationFiled: December 6, 2001Publication date: May 16, 2002Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-Ichi Sinoda
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Patent number: 5974560Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.Type: GrantFiled: January 27, 1997Date of Patent: October 26, 1999Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 5968160Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.Type: GrantFiled: September 4, 1997Date of Patent: October 19, 1999Assignee: Hitachi, Ltd.Inventors: Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura, Takashi Hotta, Yasuhiro Nakatsuka, Shigeya Tanaka, Takeshi Takemoto
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Patent number: 5784630Abstract: A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.Type: GrantFiled: January 3, 1995Date of Patent: July 21, 1998Assignee: Hitachi, Ltd.Inventors: Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura, Takashi Hotta, Yasuhiro Nakatsuka, Shigeya Tanaka, Takeshi Takemoto
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Patent number: 5640547Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.Type: GrantFiled: July 26, 1994Date of Patent: June 17, 1997Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 5623626Abstract: A logical cache memory has a logical tag and a physical tag as address tags for comparison, and status information representing their status. Data status and block status are registered at the same entry position. When access is made using a logical address, access is made to the logical tag to detect the existence of data, and when access is made using a physical address, access is made to the physical tag using an offset portion which does not depend on address conversion, to detect the existence of data.Type: GrantFiled: May 15, 1995Date of Patent: April 22, 1997Assignee: Hitachi, Ltd.Inventors: Michio Morioka, Tadaaki Bandoh, Masayuki Tanji
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Patent number: 5561775Abstract: A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations.Type: GrantFiled: December 20, 1994Date of Patent: October 1, 1996Assignee: Hitachi, Ltd.Inventors: Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka, Tadaaki Bandoh
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Patent number: 5542083Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controllled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.Type: GrantFiled: June 2, 1995Date of Patent: July 30, 1996Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 5506982Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.Type: GrantFiled: July 21, 1994Date of Patent: April 9, 1996Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 5422980Abstract: A storage area for holding instantiation is provided together with a work area in order to rapidly generate a conflict set. When a condition of a rule is met, the instantiation of the rule is stored in the storage area in a form of data structure. The instantiation having an element whose attribute has been modified in an execution part of the rule is deleted from the conflict set.Type: GrantFiled: November 3, 1993Date of Patent: June 6, 1995Assignee: Hitachi, Ltd.Inventors: Kenichi Kurosawa, Masaru Shimada, Tadaaki Bandoh, Toshihiko Nakano, Toshihiro Hayashi
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Patent number: 5404472Abstract: When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.Type: GrantFiled: November 10, 1993Date of Patent: April 4, 1995Assignee: Hitachi, Ltd.Inventors: Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka, Tadaaki Bandoh
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Patent number: 5388249Abstract: An information processing system having an original clock oscillator for delivering at least one original clock signal K defined as a first clock signal and a plurality of information processing units supplied with the original clock signal K, wherein each information processing unit comprises clock generating means for generating at least one second clock signal K.sub.1 which is phase-locked with the original clock signal K and which has a predetermined duty cycle and a logic device whose operation timing is controlled by the second clock signal K.sub.1, and the operation timing of an interface provided between at least one pair of logic devices is synchronously controlled by the clock signal K.sub.1.Type: GrantFiled: April 22, 1992Date of Patent: February 7, 1995Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh, Yasuhiro Nakatsuka, Kazuo Kato, Sin-ichi Sinoda
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Patent number: 5297239Abstract: High-speed inference method and system for a production system represented by an expert system. A knowledge base comprised of a rule and a fact possessing a plurality of attributes is converted into machine language instructions executable by a processor to execute inference. The machine language instruction of the fact has the function of transferring a value of the fact to a specified location and the machine language instruction of the rule has the function of performing matching decision by referring to the specified location. The number of pattern matching operations can be decreased and the interpretation overhead can be reduced to ensure high-speed inference.Type: GrantFiled: May 13, 1992Date of Patent: March 22, 1994Assignee: Hitachi, Ltd.Inventors: Kenichi Kurosawa, Masaru Shimada, Hirokazu Hirayama, Tadaaki Bandoh, Kiyomi Mori
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Patent number: 5287465Abstract: When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.Type: GrantFiled: July 9, 1990Date of Patent: February 15, 1994Assignee: Hitachi, Ltd.Inventors: Kenichi Kurosawa, Shigeya Tanaka, Yasuhiro Nakatsuka, Tadaaki Bandoh
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Patent number: 5274829Abstract: A data processing apparatus which allows a large number of micro instructions to be read at high speeds by storing frequently used micro instructions in the on-chip ROM and those less frequently used in the off-chip memory. From the address of the micro instruction to be accessed, it is determined whether the micro instruction is stored in the on-chip ROM or the off-chip memory, and the micro instruction is accessed on the basis of this determination. A cache memory may also be provided on the chip for providing high speed repeat access to micro instructions stored in the off-chip memory.Type: GrantFiled: October 28, 1987Date of Patent: December 28, 1993Assignee: Hitachi, Ltd.Inventors: Takashi Hotta, Yasuhiro Nakatsuka, Tadaaki Bandoh, Hideo Maejima
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Patent number: 5247649Abstract: A multi-port cache memory of multi-port memory structure is connected to and shared with a plurality of processors. The multi-port cache memory may have two sets of interface signal lines, for instruction fetch and for data read/write, to each processor. The multi-port cache memory may also be used only for data read/write. The system performance is further improved if a plurality of processors and a multi-port cache memory are fabricated on a single LSI chip.Type: GrantFiled: August 24, 1992Date of Patent: September 21, 1993Assignee: Hitachi, Ltd.Inventor: Tadaaki Bandoh
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Patent number: 5146569Abstract: Method and apparatus for instruction restart processing in a microprogram-controlled data processing apparatus, wherein, in restarting an instruction execution after instruction suspension, the internal information of the data processing apparatus at the time of instruction execution suspension is saved in a memory, and after a suspension cause removal process performed the saved internal information is recovered. A check point address associated with the address of a currently executing microprogram is stored in accordance with a designation by the microprogram. After a suspension causes removal process is performed, the execution of the instruction restarts using the check point address. If a check point address has not been stored after the suspension cause removal process is performed, the execution of the instruction restarts from a read operation of the suspended instruction from the main storage.Type: GrantFiled: March 25, 1991Date of Patent: September 8, 1992Assignee: Hitachi, Ltd.Inventors: Shinichiro Yamaguchi, Hidekazu Matsumoto, Tadaaki Bandoh, Hirokazu Hirayama, Morioka Takayuki, Soichi Takaya, Yukio Kawamoto, Jushi Ide, Yoshihiro Miyazaki