Patents by Inventor Tadahiro Imada
Tadahiro Imada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180008925Abstract: A fine particle detector includes: a casing part configured to accommodate an object to be heated; an electromagnetic wave generating part configured to generate electromagnetic waves of different frequencies; at least one power sensor configured to measure powers, from the casing part, of the electromagnetic waves that have entered into the casing part; and a fine particle detection controlling part configured to determine, based on the powers of the electromagnetic waves of the different frequencies measured by the at least one power sensor, whether an accumulated amount of fine particles accumulated in the object to be heated is greater than or equal to a predetermined accumulated amount.Type: ApplicationFiled: July 6, 2017Publication date: January 11, 2018Applicant: FUJITSU LIMITEDInventors: Tadahiro Imada, Katsusada Motoyoshi
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Publication number: 20170292420Abstract: A disclosed microwave heating apparatus includes a casing part configured to accommodate an object to be heated; a microwave generator configured to generate a microwave; an electromagnetic wave generator configured to generate an electromagnetic wave whose frequency is different from that of the microwave; an electromagnetic wave sensor configured to measure power of the electromagnetic wave, the power of the electromagnetic wave being measured after the electromagnetic wave incident on the casing part from the electromagnetic wave generator has passed through the object to be heated; and a controller configured to control, based on the power measured in the electromagnetic wave sensor, the microwave generator to generate the microwave.Type: ApplicationFiled: March 28, 2017Publication date: October 12, 2017Applicant: FUJITSU LIMITEDInventors: Tadahiro Imada, Katsusada Motoyoshi, Tatsuya Hirose, Yoichi Kawano
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Publication number: 20170204758Abstract: A particulate filter includes a particulate capturing body configured to capture particulates contained in exhaust gas, and a dielectric waveguide provided around the particulate capturing body. The effective relative permittivity of the dielectric waveguide is higher than the effective relative permittivity of the particulate capturing body.Type: ApplicationFiled: December 8, 2016Publication date: July 20, 2017Applicant: FUJITSU LIMITEDInventors: Tadahiro Imada, Yoichi Kawano
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Publication number: 20170204757Abstract: A microwave applicator includes a housing configured to contain an object of heating, multiple microwave resonators provided on and around a periphery of the housing, a microwave conductor interconnecting the microwave resonators, and a microwave generator configured to generate microwaves of different frequencies. Each microwave resonator is configured to resonate the generated microwaves of a resonant frequency of the microwave resonator, and to emit the resonated microwaves to the object of heating contained in the housing. Among the microwave resonators, a first microwave resonator and a second microwave resonator have respective resonant frequencies that are different from each other.Type: ApplicationFiled: November 29, 2016Publication date: July 20, 2017Applicant: FUJITSU LIMITEDInventor: Tadahiro Imada
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Patent number: 9647527Abstract: A power supply circuit includes a switching element and a control section. The control section converts back electromotive force generated at the time of the operation of the switching element to optical energy and converts the optical energy to an electrical signal. Furthermore, the control section drives the switching element on the basis of the electrical signal obtained by converting the optical energy. Accordingly, unlike a case where surge energy is regenerated by resonance, there is no need to use a resonant element such as an inductor. As a result, circuit scale is reduced.Type: GrantFiled: May 28, 2015Date of Patent: May 9, 2017Assignee: FUJITSU LIMITEDInventors: Tadahiro Imada, Tatsuya Hirose
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Publication number: 20170120179Abstract: A microwave irradiation apparatus includes: an annular microwave transmission path; a first microwave generation circuit that is coupled with the microwave transmission path and generates a first microwave; and a second microwave generation circuit that is coupled with the microwave transmission path and generates a second microwave; wherein the first microwave and the second microwave have frequencies equal to each other but have phases different from each other.Type: ApplicationFiled: September 13, 2016Publication date: May 4, 2017Applicant: FUJITSU LIMITEDInventor: Tadahiro Imada
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Publication number: 20170104098Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.Type: ApplicationFiled: December 21, 2016Publication date: April 13, 2017Applicant: FUJITSU LIMITEDInventors: Toshihiro OHKI, Masato NISHIMORI, Tadahiro IMADA
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Patent number: 9608083Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.Type: GrantFiled: June 9, 2015Date of Patent: March 28, 2017Assignee: FUJITSU LIMITEDInventors: Shirou Ozaki, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
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Patent number: 9564527Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type formed on one side of a semiconductor substrate; a second semiconductor layer of a second conductivity type formed on the first semiconductor layer; a third semiconductor layer of the first conductivity type formed on the second semiconductor layer; an opening part formed by removing part of the first to third semiconductor layers; a gate insulating film formed so as to cover an inner wall of the opening part; a gate electrode formed inside the opening part via the gate insulating film; a source electrode formed on a surface of the third semiconductor layer; a drain electrode connected to a part corresponding to the gate electrode on another side of the semiconductor substrate; and a fourth electrode formed on the another side of the semiconductor substrate at a part corresponding to the source electrode.Type: GrantFiled: April 24, 2013Date of Patent: February 7, 2017Assignee: FUJITSU LIMITEDInventors: Toshihiro Ohki, Masato Nishimori, Tadahiro Imada
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Patent number: 9547320Abstract: A power supply circuit includes: a depression mode transistor that includes a field plate; an enhancement mode transistor to which a source electrode and a drain electrode of the depression mode transistor are coupled; and a constant current source that is coupled to a connection node between the depression mode transistor and the enhancement mode transistor.Type: GrantFiled: August 8, 2013Date of Patent: January 17, 2017Assignee: FUJITSU LIMITEDInventor: Tadahiro Imada
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Patent number: 9515063Abstract: An electrode (109) insulated from a compound semiconductor layer (102) and being in contact with an electrode (101) and a compound semiconductor layer (103) is provided. A lattice constant of the compound semiconductor layer (103) is smaller than both of a lattice constant of the compound semiconductor layer (102) and a lattice constant of a compound semiconductor layer (104), and a lattice constant of a compound semiconductor layer (107) is smaller than both of the lattice constants of the compound semiconductor layer (102) and the lattice constants of the compound semiconductor layer (104). A conduction band energy of the compound semiconductor layer (103) is higher than a conduction band energy of the compound semiconductor layer (104).Type: GrantFiled: February 1, 2016Date of Patent: December 6, 2016Assignee: FUJITSU LIMITEDInventor: Tadahiro Imada
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Publication number: 20160315179Abstract: A compound semiconductor device includes: a substrate; a nucleation layer over the substrate; a first buffer layer over the nucleation layer; a second buffer layer between the nucleation layer and the first buffer layer, the second buffer layer containing an acceptor impurity element or a donor impurity element at a higher concentration than the first buffer layer; a carrier transit layer in contact with the first buffer layer; a carrier supply layer over the carrier transit layer; and a gate electrode, a source electrode, and a drain electrode above the carrier supply layer.Type: ApplicationFiled: March 30, 2016Publication date: October 27, 2016Applicant: FUJITSU LIMITEDInventors: Masato Nishimori, Tadahiro Imada, LEI ZHU
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Publication number: 20160224112Abstract: The present application aims at restraining an erroneous input to an input apparatus fitted to a hand for use. The input apparatus includes a touch input accepting circuit to be attached to at least any one of five fingers of a hand, and an input cancelling circuit to cancel an input to the input accepting circuit upon touching the input accepting circuit, the input cancelling circuit being attached to a finger neighboring to the finger, with the input accepting circuit attached, of the five fingers.Type: ApplicationFiled: April 8, 2016Publication date: August 4, 2016Applicant: FUJITSU LIMITEDInventor: Tadahiro Imada
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Publication number: 20160148924Abstract: An electrode (109) insulated from a compound semiconductor layer (102) and being in contact with an electrode (101) and a compound semiconductor layer (103) is provided. A lattice constant of the compound semiconductor layer (103) is smaller than both of a lattice constant of the compound semiconductor layer (102) and a lattice constant of a compound semiconductor layer (104), and a lattice constant of a compound semiconductor layer (107) is smaller than both of the lattice constants of the compound semiconductor layer (102) and the lattice constants of the compound semiconductor layer (104). A conduction band energy of the compound semiconductor layer (103) is higher than a conduction band energy of the compound semiconductor layer (104).Type: ApplicationFiled: February 1, 2016Publication date: May 26, 2016Applicant: FUJITSU LIMITEDInventor: Tadahiro IMADA
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Patent number: 9337326Abstract: A first GaN layer (2), a first AlGaN layer (3), a second GaN layer (4) and a third GaN layer (5) are formed in layers on a substrate (1). A second AlGaN layer (6) is formed on the sidewall of an opening (10A) formed in the multilayer structure. A gate electrode (8) is formed to fill an electrode trench (7a) in an insulating film (7). A portion (7c) of the insulating film (7) between the gate electrode (8) and the second AlGaN layer (6) functions as a gate insulating film. A source electrode (11) is formed above the gate electrode (8) and a drain electrode (12) is formed below the gate electrode (8). This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.Type: GrantFiled: July 29, 2015Date of Patent: May 10, 2016Assignee: FUJITSU LIMITEDInventor: Tadahiro Imada
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Patent number: 9312373Abstract: An electrode (109) insulated from a compound semiconductor layer (102) and being in contact with an electrode (101) and a compound semiconductor layer (103) is provided. A lattice constant of the compound semiconductor layer (103) is smaller than both of a lattice constant of the compound semiconductor layer (102) and a lattice constant of a compound semiconductor layer (104), and a lattice constant of a compound semiconductor layer (107) is smaller than both of the lattice constants of the compound semiconductor layer (102) and the lattice constants of the compound semiconductor layer (104). A conduction band energy of the compound semiconductor layer (103) is higher than a conduction band energy of the compound semiconductor layer (104).Type: GrantFiled: January 14, 2013Date of Patent: April 12, 2016Assignee: FUJITSU LIMITEDInventor: Tadahiro Imada
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Patent number: 9240472Abstract: A semiconductor device, that has a transistor region and a surge-protector region, includes: a substrate; a first semiconductor layer formed on the substrate; a second semiconductor layer formed on the first semiconductor layer; a gate electrode, a source electrode, and a drain electrode formed on the second semiconductor layer in the transistor region; and a surge-protector first electrode, a surge-protector second electrode, and a surge-protector third electrode formed on the second semiconductor layer in the surge-protector region, wherein the source electrode and the surge-protector second electrode are connected to each other, wherein the drain electrode and the surge-protector third electrode are connected to each other, wherein the surge-protector first electrode is formed between the surge-protector second electrode and the surge-protector third electrode, and wherein a distance between the surge-protector first electrode and the surge-protector third electrode is smaller than a distance between the gType: GrantFiled: February 28, 2013Date of Patent: January 19, 2016Assignee: FUJITSU LIMITEDInventor: Tadahiro Imada
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Publication number: 20160005848Abstract: A transistor which includes an electron transit layer and an electron supply layer which are stacked in a thickness direction of a substrate; an electron transit layer formed over the substrate in parallel to the electron transit layer and the electron supply layer; an anode electrode which forms a Schottky junction with the electron transit layer; and a cathode electrode which forms an ohmic junction with the electron transit layer are provided. The anode electrode is connected to a source of the transistor, and the cathode electrode is connected to a drain of the transistor.Type: ApplicationFiled: September 17, 2015Publication date: January 7, 2016Applicant: FUJITSU LIMITEDInventor: Tadahiro IMADA
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Publication number: 20150372587Abstract: A power supply circuit includes a switching element and a control section. The control section converts back electromotive force generated at the time of the operation of the switching element to optical energy and converts the optical energy to an electrical signal. Furthermore, the control section drives the switching element on the basis of the electrical signal obtained by converting the optical energy. Accordingly, unlike a case where surge energy is regenerated by resonance, there is no need to use a resonant element such as an inductor. As a result, circuit scale is reduced.Type: ApplicationFiled: May 28, 2015Publication date: December 24, 2015Inventors: Tadahiro Imada, Tatsuya Hirose
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Publication number: 20150333164Abstract: A first GaN layer (2), a first AlGaN layer (3), a second GaN layer (4) and a third GaN layer (5) are formed in layers on a substrate (1). A second AlGaN layer (6) is formed on the sidewall of an opening (10A) formed in the multilayer structure. A gate electrode (8) is formed to fill an electrode trench (7a) in an insulating film (7). A portion (7c) of the insulating film (7) between the gate electrode (8) and the second AlGaN layer (6) functions as a gate insulating film. A source electrode (11) is formed above the gate electrode (8) and a drain electrode (12) is formed below the gate electrode (8). This configuration enables implementation of a miniatuarizable, reliable vertical HEMT that has a sufficiently high withstand voltage and high output power and is capable of a normally-off operation without problems that could otherwise result from the use of a p-type compound semiconductor.Type: ApplicationFiled: July 29, 2015Publication date: November 19, 2015Applicant: Fujitsu LimitedInventor: Tadahiro IMADA