Patents by Inventor Tadahiro Imada

Tadahiro Imada has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120211764
    Abstract: A semiconductor device includes: a support base material, and a semiconductor element bonded to the support base material with a binder, the binder including: a porous metal material that contacts the support base material and the semiconductor element, and a solder that is filled in at least one part of pores of the porous metal material.
    Type: Application
    Filed: January 27, 2012
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED,
    Inventors: Keishiro OKAMOTO, Tadahiro IMADA, Nobuhiro IMAIZUMI, Keiji WATANABE
  • Publication number: 20120211762
    Abstract: A semiconductor device includes: a semiconductor chip having an electrode; a lead corresponding to the electrode; a metal line coupling the electrode to the lead; a first resin portion covering a coupling portion between the metal line and the electrode and a coupling portion between the metal line and the lead; and a second resin portion covering the metal line, the first resin portion, and the semiconductor chip.
    Type: Application
    Filed: December 22, 2011
    Publication date: August 23, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro IMADA, Keishiro Okamoto, Nobuhiro Imaizumi, Toshihide Kikkawa
  • Publication number: 20120199991
    Abstract: A semiconductor device includes: a semiconductor chip including a nitride semiconductor layered structure including a carrier transit layer and a carrier supply layer; a first resin layer on the semiconductor chip, the first resin layer including a coupling agent; a second resin layer on the first resin layer, the second resin layer including a surfactant; and a sealing resin layer to seal the semiconductor chip with the first resin layer and the second resin layer.
    Type: Application
    Filed: December 20, 2011
    Publication date: August 9, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Keishiro OKAMOTO, Tadahiro Imada, Nobuhiro Imaizumi, Keiji Watanabe
  • Patent number: 8198653
    Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: June 12, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Atsushi Yamada
  • Publication number: 20120139008
    Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.
    Type: Application
    Filed: February 15, 2012
    Publication date: June 7, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro IMADA, Atsushi Yamada
  • Publication number: 20120104408
    Abstract: In an aspect of a semiconductor device, there are provided a substrate, a transistor including an electron transit layer and an electron supply layer formed over the substrate, a nitride semiconductor layer formed over the substrate and connected to a gate of the transistor, and a controller controlling electric charges moving in the nitride semiconductor layer.
    Type: Application
    Filed: August 12, 2011
    Publication date: May 3, 2012
    Applicant: FUJITSU LIMITED
    Inventor: Tadahiro IMADA
  • Patent number: 8164166
    Abstract: An interfacial roughness reducing film which is in contact, on one side thereof, with an insulating film and in contact, on a side opposite from the one side, with wiring comprises a Si—O bond, and is formed using a composition containing a silicon compound that comprises at least one bond of Si—N bonds and Si—Cl bonds wherein the number of Si—N bonds and Si—Cl bonds combined per molecule of the compound is at least two. An interfacial roughness between the interfacial roughness reducing film and the wiring is smaller than that between the interfacial roughness reducing film and the insulating film.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: April 24, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata, Kouta Yoshikawa
  • Publication number: 20120091522
    Abstract: A semiconductor device includes a first semiconductor layer formed over a substrate, a second semiconductor layer formed over the first semiconductor layer, a source electrode and a drain electrode formed over the second semiconductor layer, an insulating film formed over the second semiconductor layer, a gate electrode formed over the insulating film, and a protection film covering the insulating film, the protection film being formed by thermal CVD, thermal ALD, or vacuum vapor deposition.
    Type: Application
    Filed: October 19, 2011
    Publication date: April 19, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Shirou OZAKI, Masahito Kanamura, Norikazu Nakamura, Toyoo Miyajima, Masayuki Takeda, Keiji Watanabe, Toshihide Kikkawa, Kenji Imanishi, Toshihiro Ohki, Tadahiro Imada
  • Patent number: 8143649
    Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: March 27, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Atsushi Yamada
  • Publication number: 20120056191
    Abstract: A semiconductor device includes a GaN electron transport layer provided over a substrate; a first AlGaN electron supply layer provided over the GaN electron transport layer; an AlN electron supply layer provided over the first AlGaN electron supply layer; a second AlGaN electron supply layer provided over the AlN electron supply layer; a gate recess provided in the second AlGaN electron supply layer and the AlN electron supply layer; and a gate electrode provided over the gate recess.
    Type: Application
    Filed: June 3, 2011
    Publication date: March 8, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Endo, Tadahiro Imada, Kenji Imanishi, Toshihide Kikkawa
  • Publication number: 20120049244
    Abstract: A semiconductor device includes: a substrate; a semiconductor stacked structure, provided over the substrate, including an electron transit layer and an electron supply layer; a gate electrode, a source electrode, and a drain electrode provided over the semiconductor stacked structure; a gate pad, a source pad, and a drain pad provided over the gate electrode, the source electrode, and the drain electrode, and connected to the gate electrode, the source electrode, and the drain electrode, respectively; and a conductive layer provided under the gate pad, the source pad, and the drain pad, wherein a distance between the gate pad and the source pad is smaller than a distance between the gate pad and the drain pad.
    Type: Application
    Filed: October 6, 2011
    Publication date: March 1, 2012
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Kazukiyo Joshin
  • Patent number: 8089138
    Abstract: A surface-hydrophobicized film is provided which is in contact with an insulating film, and has a higher hydrophobicity than the insulating film at the time of the contact, and which is in contact, on an opposite side of the surface-hydrophobicized film, with wiring, and contains at least one atom selected from the group consisting of sulfur atoms, phosphorus atoms and nitrogen atoms. Semiconductor devices with wiring layers having a low leakage current, a high EM resistance and a high TDDB resistance can be manufactured by using the film.
    Type: Grant
    Filed: August 21, 2009
    Date of Patent: January 3, 2012
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata
  • Publication number: 20110207319
    Abstract: The method of manufacturing the semiconductor device includes forming an insulating film above a semiconductor substrate, forming an opening in the insulating film, forming a conductive film above the insulating film with the opening formed, removing the conductive film above the insulating film to bury the conductive film in the opening, and processing a surface of the insulating film with a silicon compound including Si—N or Si—Cl.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 25, 2011
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Kouta Yoshikawa
  • Publication number: 20110193096
    Abstract: An n-type GaN layer (3), a GaN layer (7) formed over the n-type GaN layer (3), an n-type AlGaN layer (9) formed over the GaN layer (7), a gate electrode (15) and a source electrode (13) formed over the n-type AlGaN layer (9), a drain electrode (14) formed below the n-type GaN layer (3), and a p-type GaN layer (4) formed between the GaN layer (7) and the drain electrode (14) are provided.
    Type: Application
    Filed: April 21, 2011
    Publication date: August 11, 2011
    Applicant: FUJITSU LIMITED
    Inventor: Tadahiro IMADA
  • Patent number: 7928536
    Abstract: Techniques for obtaining a wiring layer with a high TDDB resistance and little leakage current, and accordingly, for manufacturing a highly reliable semiconductor device with a small electric power consumption are provided, in which an interfacial roughness reducing film is formed which is in contact with an insulator film and also in contact with a wiring line on the other side surface thereof, and has an interfacial roughness between the wiring line and the interfacial roughness reducing film smaller than that between the insulator film and the interfacial roughness reducing film.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: April 19, 2011
    Assignee: Fujitsu Limited
    Inventors: Tadahiro Imada, Yoshihiro Nakata, Ei Yano
  • Publication number: 20100320618
    Abstract: An interconnection substrate including: a first insulating film made of a silicon compound, an adhesion enhancing layer formed on the first insulating film, and a second insulting film made of a silicon compound and formed on the adhesion enhancing layer, wherein the first insulating film and the second insulating film are combined together with a component having a structure represented by General Formula (1) described below: Si—CXHY—Si??General Formula (1) where X is equal to 2Y and is an integer of 1 or more.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 23, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Shirou Ozaki, Yoshihiro Nakata, Tadahiro Imada, Yasushi Kobayashi
  • Patent number: 7830013
    Abstract: The present invention aims at providing: a material for forming an adhesion reinforcing layer which can reinforce the adhesion between a low dielectric constant film, especially a low dielectric constant film containing an inorganic material, and other members; an adhesion reinforcing layer formed by the said material and exhibits superior adhesion; a fast and highly reliable semiconductor device having the adhesion reinforcing layer; and a manufacturing method thereof. The material for forming an adhesion reinforcing layer contains at least any one of organoalkoxysilane having a basic functional group, a basic additive and organoalkoxysilane. The adhesion reinforcing layer is formed by the said material. The manufacturing method of a semiconductor device includes a process for forming a low dielectric constant film and, at least before or after the process for forming a low dielectric constant film, a process for forming an adhesion reinforcing layer with the said material.
    Type: Grant
    Filed: April 3, 2006
    Date of Patent: November 9, 2010
    Assignee: Fujitsu Limited
    Inventors: Junichi Kon, Ei Yano, Yoshihiro Nakata, Tadahiro Imada
  • Publication number: 20100163928
    Abstract: An i-GaN layer (electron transit layer), an n-GaN layer (compound semiconductor layer) formed over the i-GaN layer (electron transit layer), and a source electrode, a drain electrode and a gate electrode formed over the n-GaN layer (compound semiconductor layer) are provided. A recess portion is formed inside an area between the source electrode and the drain electrode of the n-GaN layer (compound semiconductor layer) and at a portion separating from the gate electrode.
    Type: Application
    Filed: November 13, 2009
    Publication date: July 1, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Tadahiro Imada, Atsushi Yamada
  • Publication number: 20100133692
    Abstract: A silicic coating of 2.4 g/cm3 or higher density, obtained by forming a silicic coating precursor with the use of at least one type of silane compound having a photosensitive functional group and thereafter irradiating the silicic coating precursor with at least one type of light. This silicic coating can be used as a novel barrier film or stopper film for semiconductor device.
    Type: Application
    Filed: February 4, 2010
    Publication date: June 3, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Yasushi Kobayashi, Kouta Yoshikawa, Yoshihiro Nakata, Tadahiro Imada, Shirou Ozaki
  • Publication number: 20100007031
    Abstract: The invention provides an agent for post-etch treating a silicon dielectric film, including: at least one nitrogen-containing substance selected from the group consisting of ammonium bases and amine compounds; an acid; and at least one silicon-containing compound containing silicon, carbon and hydrogen. According to the present invention, it becomes possible to suppress an increase in the dielectric constant of a silicon dielectric film caused by etching.
    Type: Application
    Filed: September 15, 2009
    Publication date: January 14, 2010
    Applicant: FUJITSU LIMITED
    Inventors: Yasushi Kobayashi, Kouta Yoshikawa, Yoshihiro Nakata, Tadahiro Imada, Shirou Ozaki