Patents by Inventor Tadahiro Kuroda

Tadahiro Kuroda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20010011918
    Abstract: The disclosed semiconductor integrated circuit device can control the threshold thereof without adding any other supply voltages except a drive supply voltage and a ground supply voltage. The semiconductor integrated circuit device comprises: a substrate potential generating circuit operative on the basis of a control signal, for deepening a substrate bias by pumping out charges from a semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; and a switch circuit operative on the basis of the control signal and turned on when the substrate potential generating circuit is deactivated, to set potential of the semiconductor substrate to a supply potential, but turned off when the substrate potential generating circuit is activated.
    Type: Application
    Filed: November 9, 1999
    Publication date: August 9, 2001
    Inventor: TADAHIRO KURODA
  • Patent number: 6222391
    Abstract: A circuit for shifting the potential level of an input signal toward higher potentials is added to a conventional differential ECL circuit in order to shift levels of emitter potentials of npn bipolar transistors forming a current switch toward higher potentials. Thus, the ECL circuit is improved to ensure a continuous flow of a current and to maintain stable operations even at an instant where base potentials of the npn bipolar transistors are switched by a standard ECL-level signal even when the power source voltage is around −2 V.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: April 24, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Tadahiro Kuroda
  • Patent number: 6215159
    Abstract: CMOS logic circuit CM is of a structure in which the threshold value of constituent transistors MP1, MN1, etc. thereof is set to value lower than ordinary value, and the threshold value of a stand-by state current control P-channel MOS transistor MP2 is set to value higher than the threshold value of the transistors MP1, MN1, etc. constituting the CMOS logic circuit CM. A level conversion circuit 10 outputs a signal in which low level indicates negative voltage and high level indicates the same potential VDD as that of the first power supply line P1 in dependency upon high level and low level of signal applied to control input terminal SIG to thereby carry out ON/OFF control of the P-channel MOS transistor MP2.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: April 10, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuya Fujita, Gensoh Matsubara, Tadahiro Kuroda, Takayasu Sakurai
  • Patent number: 6204707
    Abstract: A flip-flop circuit 10 is provided with a discord detecting circuit DDC and a clock control circuit CCC. The discord detecting circuit DDC detects the discord of a data input signal DIS of the flip-flop circuit 10 with a data output signal DOS thereof. When the data input signal DIS discords with the data output signal DOS, the clock control circuit CCC supplies a short pulse to the flip-flop circuit 10 as an internal clock signal ICLK in synchronism with the rising of an external clock signal ECLK. On the other hand, when the data input signal DIS coincides with the data output signal DOS, the clock control circuit CCC supplies a low level signal to the flip-flop circuit 10 as the internal clock signal ICLK. Thus, it is possible to suppress electric power consumption required to supply a clock signal, and to prevent errors from being caused in a flip-flop operation.
    Type: Grant
    Filed: August 26, 1999
    Date of Patent: March 20, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tadahiro Kuroda
  • Patent number: 6187602
    Abstract: The disclosed device and method can inspect the CMOS integrated circuit devices at high precision on the basis of the static current of the voltage supply connected thereto. A CMOS integrated circuit comprises: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.
    Type: Grant
    Filed: March 8, 2000
    Date of Patent: February 13, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6166562
    Abstract: A driving voltage supplied to a semiconductor integrated circuit can be controlled. The semiconductor integrated circuit device provided with a voltage converter circuit comprises: a buffer circuit having: a P-channel MOS transistor having a source connected to a first supply voltage; and an N-channel MOS transistor having a source connected to a second supply voltage and a drain connected to a drain of the P-channel MOS transistor, an output voltage being outputted from a common-connected drain terminals of the two MOS transistors; a duty ratio control circuit having: a counter for outputting a first n-bit signal by repeatedly counting up numbers from 0 to (2.sup.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: December 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinji Mita, Kojiro Suzuki, Tadahiro Kuroda
  • Patent number: 6124752
    Abstract: The disclosed semiconductor integrated circuit device can control the threshold thereof without adding any other supply voltages except a drive supply voltage and a ground supply voltage. The semiconductor integrated circuit device comprises: a substrate potential generating circuit operative on the basis of a control signal, for deepening a substrate bias by pumping out charges from a semiconductor substrate when activated, but for setting an output thereof to a high impedance when deactivated; and a switch circuit operative on the basis of the control signal and turned on when the substrate potential generating circuit is deactivated, to set potential of the semiconductor substrate to a supply potential, but turned off when the substrate potential generating circuit is activated.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: September 26, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6081153
    Abstract: A master slave type flip-flop circuit having a master latch circuit ML and a slave latch circuit SL has a voltage level converter circuit 20 in the slave latch circuit SL to reduce the number of elements used in the circuit, which results in reducing the power consumption and in increasing the operation speed of the circuit.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: June 27, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mototsugu Hamada, Tadahiro Kuroda
  • Patent number: 6051442
    Abstract: The disclosed device and method can inspect the CMOS integrated circuit devices at high precision on the basis of the static current of the voltage supply connected thereto. A CMOS integrated circuit comprises: at least one CMOS circuit having at least one P-channel MOS transistor and at least one N-channel MOS transistor; a first pad connected to a source of the P-channel MOS transistor; a second pad connected to a source of the N-channel MOS transistor; a third pad connected to an N-type substrate or an N-type well formed with the P-channel MOS transistor; and a fourth pad connected to a P-type substrate or a P-type well formed with the N-channel MOS transistor.
    Type: Grant
    Filed: April 2, 1997
    Date of Patent: April 18, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6037805
    Abstract: To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first supply voltage and the second supply voltage.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro Kuroda, Takayasu Sakurai
  • Patent number: 6023186
    Abstract: A CMOS integrated circuit device enabling accurate inspection of its static power source current includes: a CMOS circuit having a p-channel MOS transistor and an n-channel MOS transistor; a first pad connected to the source of the p-channel MOS transistor; a second pad connected to the source of the n-channel MOS transistor; a p-type diffused region formed in an n-type substrate or n-well having formed the p-channel MOS transistor; an n-type diffused region formed in the p-type substrate or p-well having formed the n-channel MOS transistor; a third pad connected through the p-type diffused region to the n-type substrate or n-well having formed the p-channel MOS transistor; and a fourth pad connected through the n-type diffused region to the p-type substrate or p-well having formed the n-channel MOS transistor.
    Type: Grant
    Filed: July 24, 1998
    Date of Patent: February 8, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 6011713
    Abstract: A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data.
    Type: Grant
    Filed: December 22, 1997
    Date of Patent: January 4, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Fumiyuki Yamane, Tadahiro Kuroda, Toshinari Takayanagi, Masataka Matsui, Yasuo Unekawa, Tetsu Nagamatsu
  • Patent number: 6005265
    Abstract: A semiconductor integrated circuit device capable of reducing delay of wiring as far as possible is provided. The semiconductor integrated circuit device comprises at least two sets of pairs of signal lines having first polarity and second polarity opposite thereto, wherein the signal line of the first polarity of the signal lines of the second set is disposed at the portion adjacent to the signal line of the first polarity of the signal lines of the first set, the signal line of the second polarity of the first set is disposed at the portion adjacent to the signal line of the first polarity of the second set, and the signal line of the second polarity of the second set is disposed at the portion adjacent to the signal line of the second polarity of the first set.
    Type: Grant
    Filed: September 29, 1997
    Date of Patent: December 21, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 5969536
    Abstract: The semiconductor device includes a circuit, such as, an ECL circuit for comparing input signals with a reference potential determined as a circuit threshold value and outputting an output signal according to the comparison result. The semiconductor device further includes a switching circuit for switching the reference potential level between ordinary operation and burn-in operation of the ECL circuit. The time required for the burn-in operation can be reduced markedly.
    Type: Grant
    Filed: February 13, 1997
    Date of Patent: October 19, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro Kuroda, Makoto Noda
  • Patent number: 5959472
    Abstract: In the constant current drive type driver used for an LVDS (low voltage differential signal) interface, the parasitic capacitance of the package pins is charged and discharged sufficiently at a high speed to secure the high speed signal transmission operation. Further, the AC differential amplitude large enough to be received by the receiver can be obtained. The driver circuit device comprises: a transmit circuit composed of transistors (52, 53, 56, 57) for transmitting a signal by switching the signal current direction flowing through a pair of transmission lines (8, 9) connected between two output terminals (13 and 13B); and a constant current source composed of transistors (54, 75) for controlling the current value of the transmit circuit. In the idle state, only one of the two transistors (54 and 75) of the constant current source is turned on to limit the signal current flowing through the output terminals (13 and 13B).
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: September 28, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Tadahiro Kuroda
  • Patent number: 5936436
    Abstract: The disclosed substrate potential detecting circuit can reduce both the power consumption and the pattern area thereof. The substrate potential detecting circuit comprises: a series circuit composed of a plurality of same-conductivity type MOS transistors. Each transistor has a source terminal connected to a substrate terminal thereof and a drain terminal connected to a gate terminal thereof. Further, the channel widths of all the MOS transistors are determined equal to each other and so selected that all the transistors can be operative in a sub-threshold region, respectively.
    Type: Grant
    Filed: January 24, 1997
    Date of Patent: August 10, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 5933029
    Abstract: To minimize the power consumption, the disclosed semiconductor integrated circuit device, comprises; a bias circuit for generating a predetermined voltage fixed between a first supply voltage and a second supply voltage; a driver circuit for receiving an inversion input signal and a non-inversion input signal each vibrating between the first and second supply voltages, for converting the received input signals into a signal vibrating between an output voltage of the bias circuit and the first supply voltage, and for driving a transfer path by the converted signal; a voltage divider circuit for dividing an output voltage of the bias circuit; and a receiver circuit for detecting the signal for driving the transfer path by use of an output of the voltage divider circuit as a reference voltage, and for converting the detected signal into a signal vibrating between the first/supply voltage and the second supply voltage.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: August 3, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro Kuroda, Takayasu Sakurai
  • Patent number: 5929693
    Abstract: The semiconductor integrated circuit device can control the threshold voltage of MOSFETs at a low value while keeping the variation thereof at a small level in operation mode, but switches the threshold voltage thereof from the low value to a high value in standby mode. The semiconductor integrated circuit device comprises: a detecting circuit for detecting a physical quantity (e.g., substrate bias) of a semiconductor substrate and for outputting n-units (n.gtoreq.
    Type: Grant
    Filed: January 28, 1997
    Date of Patent: July 27, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tadahiro Kuroda
  • Patent number: 5834967
    Abstract: A semiconductor integrated circuit device includes a leak detection circuit which can be realized by small pattern area provides voltage Vb through two transistors M1n and M2n, which are caused to be operative in the sub-threshold area without use of a resistor at the gate of a leak current detection transistor MLn. The leak current detection magnification does not become dependent upon power supply voltage and temperature. Thus, detection of the leakage current can be precisely carried out.
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: November 10, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadahiro Kuroda, Tetsuya Fujita
  • Patent number: 5764086
    Abstract: The comparator circuit comprises a first comparator circuit having a differential input stage composed of P-channel FETs; a second comparator circuit having a differential input stage composed of N-channel FETs; pull-up and pull-down resistances connected to the output terminals of the two comparator circuits, respectively; at least one skew adjusting circuit having a delay circuit and a selector; and a logical gate for obtaining the two output signals of the two comparator circuits. Since the two differential input signals can be received by the two comparator circuits and according to the potentials of the two differential input signals, even if the supply potential is low, the comparator circuit can compare the two differential input signals in a wide potential range from the ground potential and the supply potential, so that it is possible to provide a high speed interface circuit which can satisfy the LVDS standard at a low supply potential.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: June 9, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsu Nagamatsu, Tadahiro Kuroda