Patents by Inventor Tadao Nakamura

Tadao Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210381405
    Abstract: An oil pump includes a pump component, a valve container, a valve mechanism, and a circumvention passage. The valve container includes a through hole establishing communication between an inside and an outside of the valve container. The valve mechanism includes: a valve body contained in the valve container; a valve element contained movably in the valve body; a back pressure chamber disposed to face a first valve end of the valve element; a drive mechanism disposed to face a second valve end of the valve element and structured to generate a drive force to move the valve element; and an aperture positioned higher in a vertical direction than the through hole and formed in the valve body so as to establish communication between the back pressure chamber and the inside of the valve container. The circumvention passage establishes communication between the through hole and the aperture.
    Type: Application
    Filed: September 10, 2019
    Publication date: December 9, 2021
    Inventors: Koji SAGA, Tadao NAKAMURA
  • Patent number: 11164612
    Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 2, 2021
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20200409277
    Abstract: The present invention provides a measurement apparatus that measures a position of an object which includes a first mark and a second mark, comprising: an image capturing unit configured to capture the first mark and the second mark in a state in which the first mark and the second mark are contained in a field of view; and a polarizing element configured to generate different polarization directions from each other in light from the first mark and in light from the second mark which are incident on the image capturing unit.
    Type: Application
    Filed: June 19, 2020
    Publication date: December 31, 2020
    Inventors: Takamitsu Komaki, Tadao Nakamura
  • Patent number: 10867647
    Abstract: A marching memory includes an alternating periodic array of odd-numbered columns (U1, U2, . . . , Un?1, Un) and even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn). Each of the odd-numbered columns (U1, U2, . . . , Un?1, Un) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: December 15, 2020
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20200331190
    Abstract: The present invention provides an imprint apparatus for performing an imprint process of forming a pattern of an imprint material on a substrate using a mold, including an adjustment unit configured to adjust a shape of the mold, and a control unit configured to control the imprint process, wherein the control unit obtains information indicating a tendency concerning a change of the shape of the mold corresponding to a use count of the mold used for the imprint process, and performs the imprint process while correcting the shape of the mold by the adjustment unit in accordance with the use count of the mold based on the information.
    Type: Application
    Filed: April 13, 2020
    Publication date: October 22, 2020
    Inventors: Tadao Nakamura, Takamitsu Komaki, Kiyohito Yamamoto
  • Publication number: 20200152247
    Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20200143857
    Abstract: A marching memory includes an alternating periodic array of odd-numbered columns (U1, U2, . . . , Un?1, Un) and even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn). Each of the odd-numbered columns (U1, U2, . . . , Un?1, Un) has a sequence of front-stage cells aligned along a column direction so as to store a set of moving information of byte size or word size. And each of the even-numbered columns (Ur1, Ur2, . . . , Urn?1, Urn) has a sequence of rear-stage cells aligned along a column direction so as to store the set of moving information, so that the set of moving information can be transferred synchronously, step by step, along a direction orthogonal to the column direction.
    Type: Application
    Filed: January 23, 2019
    Publication date: May 7, 2020
    Inventors: Tadao NAKAMURA, Michael J. FLYNN
  • Patent number: 10573359
    Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: February 25, 2020
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Patent number: 10394134
    Abstract: The present invention provides an exposure method for repeatedly performing an exposure process for exposing a substrate via a projection optical system, the method comprising a first exposure process for measuring optical characteristics of the projection optical system, and exposing the substrate while correcting the optical characteristics based on a result of the measurement; a second exposure process for exposing the substrate while correcting the optical characteristics based on a result of estimating the optical characteristics by a prediction formula, wherein the first exposure process is repeatedly performed, and the second exposure process is started after the first exposure process where it is judged that the determined coefficient of the prediction formula has converged.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: August 27, 2019
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Ryo Koizumi, Tadao Nakamura
  • Publication number: 20190041759
    Abstract: The present invention provides an exposure method for repeatedly performing an exposure process for exposing a substrate via a projection optical system, the method comprising a first exposure process for measuring optical characteristics of the projection optical system, and exposing the substrate while correcting the optical characteristics based on a result of the measurement; a second exposure process for exposing the substrate while correcting the optical characteristics based on a result of estimating the optical characteristics by a prediction formula, wherein the first exposure process is repeatedly performed, and the second exposure process is started after the first exposure process where it is judged that the determined coefficient of the prediction formula has converged.
    Type: Application
    Filed: July 31, 2018
    Publication date: February 7, 2019
    Inventors: Ryo Koizumi, Tadao Nakamura
  • Patent number: 9599903
    Abstract: A foreign substance detection method includes: judging the presence/absence of a foreign substance by measuring a surface condition of a substrate; measuring a surface condition of a second substrate different from the substrate upon replacing the substrate on the chuck with the second substrate, when it is judged in the judging that a foreign substance exists; and determining whether an adhering location of the foreign substance determined to exist in the judging is the substrate, based on a measurement result obtained in the measurement.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: March 21, 2017
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Tadao Nakamura, Yuji Kosugi, Tomohisa Nakazawa
  • Patent number: 9449696
    Abstract: A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: September 20, 2016
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Patent number: 9361957
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: June 7, 2016
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20160118124
    Abstract: A direct-transfer marching memory includes an array of memory units, each of the memory units having a sequence of bit-level cells so as to store information of byte size or word size, the information of byte size or word size is transferred synchronously, step by step, along a direction orthogonal to a direction of the sequence of bit-level cells, each of the bit-level cells encompassing an electron-storage region configured to accumulate cell-electrons. The cell-electrons accumulated in an electron-storage region in a subject memory unit is directly transferred to an adjacent electron-storage region, which is assigned in the next memory unit adjacent to the subject memory unit, the transfer of the cell-electrons is directly controlled by control signals, without using a combinational function of a logic gate circuit.
    Type: Application
    Filed: October 7, 2015
    Publication date: April 28, 2016
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20150149718
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Application
    Filed: November 25, 2014
    Publication date: May 28, 2015
    Inventors: Tadao NAKAMURA, Michael J. Flynn
  • Publication number: 20150131065
    Abstract: A foreign substance detection method includes: judging the presence/absence of a foreign substance by measuring a surface condition of a substrate; measuring a surface condition of a second substrate different from the substrate upon replacing the substrate on the chuck with the second substrate, when it is judged in the judging that a foreign substance exists; and determining whether an adhering location of the foreign substance determined to exist in the judging is the substrate, based on a measurement result obtained in the measurement.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 14, 2015
    Inventors: Tadao NAKAMURA, Yuji KOSUGI, Tomohisa NAKAZAWA
  • Patent number: 8949650
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Grant
    Filed: July 20, 2010
    Date of Patent: February 3, 2015
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Publication number: 20140344544
    Abstract: A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.
    Type: Application
    Filed: August 4, 2014
    Publication date: November 20, 2014
    Inventors: Tadao Nakamura, Michael J. Flynn
  • Patent number: 8625069
    Abstract: An exposure apparatus the present invention comprises: an illumination optical system configured to illuminate an illumination area on an original with light from a light source; a projection optical system configured to project a pattern of the original onto a substrate; a first stage configured to hold the original; a second stage configured to hold the substrate; and a controller configured to control driving of at least one of the first stage, the second stage, and an optical element which forms the projection optical system so as to reduce variations in imaging characteristics of the projection optical system, based on a dependence of a transmittance of the pattern on a position in the illumination area.
    Type: Grant
    Filed: June 18, 2008
    Date of Patent: January 7, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Nobuhiko Yabu, Tadao Nakamura
  • Publication number: 20120117412
    Abstract: A computer system encompasses a processor (11) including a control unit (111) and an ALU (112) configured to execute arithmetic and logic operations synchronized with the clock signal, and a marching main memory (31), which embraces an array of memory units, configured to store information in each of memory units and to transfer synchronously with the clock signal, providing the processor (11) with the stored information actively and sequentially so that the ALU (112) can execute the arithmetic and logic operations with the stored information. The results of the processing in the ALU (112) are sent out to the marching main memory (31), but there is only one way of instructions flow from the marching main memory (31) to the processor.
    Type: Application
    Filed: July 20, 2010
    Publication date: May 10, 2012
    Inventors: Tadao Nakamura, Michael J. Flynn