Patents by Inventor Tadashi Iguchi

Tadashi Iguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373327
    Abstract: A method of producing a semiconductor memory device includes, when three directions crossing each other are set to first, second, and third directions, respectively, laminating a plurality of first laminates and a plurality of second laminates on a semiconductor substrate in the third direction. The method further includes forming ends of the plurality of first laminates in shapes of steps extending in the first direction, and forming ends of the plurality of second laminates in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20200135750
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: December 31, 2019
    Publication date: April 30, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Patent number: 10610784
    Abstract: A non-transitory computer-readable information storage medium storing a program that causes a computer to implement a game in which a first area of a virtual space that includes a maze-shaped path delimited by given virtual walls is allocated to a first player character that moves under the control of a first player, a second area of the virtual space is allocated to a second player character that moves under the control of a second player, and the first player character and the second player character compete for game progress in the respective areas allocated thereto.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: April 7, 2020
    Assignee: BANDAI NAMCO ENTERTAINMENT INC.
    Inventors: Toru Takahashi, Tadashi Iguchi
  • Patent number: 10553600
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10515997
    Abstract: A memory device according to an embodiment includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer parallel to a first direction and a second direction perpendicular to the first direction, and stacked in a third direction perpendicular to the first direction; a first, electrode connected to the first conductive layer; a second electrode connected to the second conductive layer; a third electrode connected to the third conductive layer; and a fourth electrode connected to the fourth conductive layer. The third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode. The fourth conductive layer is not provided between the second electrode and the third electrode. A region without the second conductive layer is provided between the second electrode and the third electrode.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: December 24, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tadashi Iguchi
  • Publication number: 20190296080
    Abstract: A memory device according to an embodiment includes: a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer parallel to a first direction and a second direction perpendicular to the first direction, and stacked in a third direction perpendicular to the first direction; a first, electrode connected to the first conductive layer; a second electrode connected to the second conductive layer; a third electrode connected to the third conductive layer; and a fourth electrode connected to the fourth conductive layer. The third conductive layer and the fourth conductive layer are not provided between the first electrode and the second electrode. The fourth conductive layer is not provided between the second electrode and the third electrode. A region without the second conductive layer is provided between the second electrode and the third electrode.
    Type: Application
    Filed: September 20, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Tadashi IGUCHI
  • Publication number: 20190296082
    Abstract: A memory device according to an embodiment includes: a first conductive layer extending in a first direction; a second conductive layer extending in the first direction; a third conductive layer extending in a second direction intersecting the first direction, the third conductive layer being provided between the first conductive layer and the second conductive layer; a fourth conductive layer that extends in the second direction and is provided between the first conductive layer and the second conductive layer; a first connection portion connecting a first end portion of the third conductive layer and a first end portion of the fourth conductive layer; and a first resistance change layer provided between the first conductive layer and the third conductive layer.
    Type: Application
    Filed: September 20, 2018
    Publication date: September 26, 2019
    Applicant: Toshiba Memory Corporation
    Inventor: Tadashi IGUCHI
  • Publication number: 20190074294
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Tadashi IGUCHI, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Patent number: 10186520
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array that includes memory cells and a plurality of first conducting layers. The memory cells are arrayed in a three-dimensional manner. The first conducting layers are connected to the memory cells and are arrayed in a laminating direction. Stepped wiring portion includes a plurality of second conducting layers. The plurality of second conducting layers connect the first conducting layers and external circuits. At least one of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the first side portion side. Other ones of the plurality of second conducting layers includes a contact formation area on a top surface thereof in the stepped wiring portion positioned on the second side portion side.
    Type: Grant
    Filed: September 2, 2016
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tadashi Iguchi
  • Patent number: 10147735
    Abstract: A semiconductor memory device according to an embodiment includes a memory cell array configured to have a memory string obtained by connecting first selection transistors, memory transistors, and second selection transistors in series. When three directions crossing each other are set to first, second, and third directions, respectively, the memory cell array has first conductive layers to be control gates of the first selection transistors, second conductive layers to be control gates of the memory transistors, and third conductive layers to be control gates of the second selection transistors, which are laminated in the third direction. Ends of the first conductive layers and ends of the third conductive layers are formed in shapes of steps extending in the first direction and ends of the second conductive layers are formed in shapes of steps extending in both directions of the first direction and the second direction.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 4, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Tadashi Iguchi, Murato Kawai, Toru Matsuda, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20180178126
    Abstract: A non-transitory computer-readable information storage medium storing a program that causes a computer to implement a game in which a first area of a virtual space that includes a maze-shaped path delimited by given virtual walls is allocated to a first player character that moves under the control of a first player, a second area of the virtual space is allocated to a second player character that moves under the control of a second player, and the first player character and the second player character compete for game progress in the respective areas allocated thereto.
    Type: Application
    Filed: December 19, 2017
    Publication date: June 28, 2018
    Applicant: BANDAI NAMCO ENTERTAINMENT INC.
    Inventors: Toru TAKAHASHI, Tadashi IGUCHI
  • Publication number: 20180182773
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Patent number: 9993731
    Abstract: A computer performs a process for displaying an object string and a player object within a game screen, the object string including a main object, and at least one sub-object that is connected to the main object, the player object being an object that can be operated by a player, and virtual walls that limit a moving direction of each of the main object, the sub-object and the player object being provided within the game screen. The motion of the player object within the game screen is controlled in response to an operation performed by the player. The motion mode of the object string is switched from a first mode to a second mode or a third mode based on a given condition, the second mode being a mode in which the object string is inferior as compared with the first mode, and the third mode being a mode in which the main object is superior as compared with the first mode.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: June 12, 2018
    Assignee: BANDAI NAMCO Entertainment Inc.
    Inventor: Tadashi Iguchi
  • Patent number: 9997526
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 12, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Gaku Sudo, Masanobu Baba, Megumi Ishiduki, Tadashi Iguchi, Murato Kawai
  • Patent number: 9947681
    Abstract: According to one embodiment, a method for manufacturing a semiconductor device is disclosed. The method includes forming a stacked body alternately stacked with a plurality of members and a plurality of intermediate bodies having materials different from materials of the plurality of members, processing an end portion of at least two layers of the plurality of members sequentially in a stacking direction of the stacked body, and forming a step-wise step stacked with the plurality of members and the plurality of intermediate bodies, forming a plurality of side wall films contacting the step and making the end portion of the plurality of members in a step-wise. The making the end portion of the plurality of members in a step-wise includes retreating a portion of the plurality of members, the portion separated from the plurality of side wall films and exposed from the stacked body.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: April 17, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Gaku Sudo, Masanobu Baba, Megumi Ishiduki, Tadashi Iguchi, Murato Kawai
  • Patent number: 9935118
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Takuya Inatsuka, Tadashi Iguchi, Murato Kawai, Hisashi Kato, Megumi Ishiduki
  • Publication number: 20180083025
    Abstract: A semiconductor memory device includes a gate insulating film on a semiconductor substrate, a memory cell array in a memory cell region, a first transistor in a peripheral circuit region which surrounds the memory cell region, a second transistor in a scribe region which surrounds the peripheral circuit region, a first stepped structure in the memory cell region, a second stepped structure in the peripheral circuit region facing the first stepped structure, and an interlayer insulating film between the first and second stepped structures. Each of the first and second stepped structures includes a plurality of insulating layers and conductive layers that are alternately stacked on the semiconductor substrate, and an upper surface of an uppermost layer of the first stepped structure, an upper surface of an uppermost layer of the second stepped structure, and an upper surface of the interlayer insulating film are formed on the same plane.
    Type: Application
    Filed: August 28, 2017
    Publication date: March 22, 2018
    Inventors: Takuya INATSUKA, Tadashi IGUCHI
  • Publication number: 20180076211
    Abstract: According to one embodiment, a semiconductor memory device includes a first conductive layer, a first semiconductor body, a second semiconductor body, a first memory layer, and a second memory layer. The first conductive layer includes first to fourth extension regions, and a first connection region. The first extension region extends in a first direction. The second extension region extends in the first direction and is arranged with the first extension region in the first direction. The third extension region extends in the first direction and is arranged with the first extension region in a second direction crossing the first direction. The fourth extension region extends in the first direction, is arranged with the third extension region in the first direction, and is arranged with the second extension region in the second direction.
    Type: Application
    Filed: March 17, 2017
    Publication date: March 15, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Takuya INATSUKA, Tadashi IGUCHI, Murato KAWAI, Hisashi KATO, Megumi ISHIDUKI
  • Patent number: 9793287
    Abstract: A semiconductor wafer including first and second stacked bodies provided on separate parts of a substrate. The first stacked body includes a first insulating and a second insulating film being provided on the first portion, the second stacked body includes a plurality of third insulating films and a plurality of electrode films. The third insulating films and the electrode films are alternately stacked, and a shape of an end portion of the second stacked body on a side opposing to the first stacked body is a stepped pattern.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: October 17, 2017
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Tadashi Iguchi
  • Publication number: 20170239570
    Abstract: A computer performs a process for displaying an object string and a player object within a game screen, the object string including a main object, and at least one sub-object that is connected to the main object, the player object being an object that can be operated by a player, and virtual walls that limit a moving direction of each of the main object, the sub-object and the player object being provided within the game screen. The motion of the player object within the game screen is controlled in response to an operation performed by the player. The motion mode of the object string is switched from a first mode to a second mode or a third mode based on a given condition, the second mode being a mode in which the object string is inferior as compared with the first mode, and the third mode being a mode in which the main object is superior as compared with the first mode.
    Type: Application
    Filed: February 17, 2017
    Publication date: August 24, 2017
    Inventor: Tadashi IGUCHI