Patents by Inventor Tadashi Maruyama
Tadashi Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240120406Abstract: It is related to improving a performance of a semiconductor device and suppressing yield deterioration. Using a resist pattern as a mask, an ion-implantation is performed from an upper surface of a semiconductor substrate to form an ion-implanted layer in the semiconductor substrate. By subsequently, another ion-implantation is performed. Then, another ion-implanted layer is formed in the semiconductor substrate so as to overlap with the ion-implanted layer. Next, a heat treatment is performed on the semiconductor substrate to diffuse impurities contained in the ion-implanted layers, thereby an p-type floating region is formed.Type: ApplicationFiled: August 15, 2023Publication date: April 11, 2024Inventors: Tadashi YAMAGUCHI, Yoshiki MARUYAMA
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Publication number: 20240068884Abstract: A thermosensitive part sensing temperature; a temperature sensor for measurement provided in the unit and measuring temperature by contacting the unit with a body to be measured; a temperature detecting part detecting, from when the unit contacts the body, the time when the sensor senses a difference from an initial temperature of the sensor, and a measured temperature of the sensor at that time, and detecting, from when the difference is sensed, a time after a certain length of time and a measured temperature of the sensor at that time; an estimating part estimating, from the time when the difference is sensed and a time after a certain length of time, the time when the thermosensitive part contacts the body, and the measured temperature at that time; and a heat conduction analyzing part estimating the measured temperature based on output information from the temperature detecting part and the estimating part.Type: ApplicationFiled: January 12, 2022Publication date: February 29, 2024Applicants: SEMITEC Corporation, National Institute of Technology, HIROSAKI UNIVERSITYInventors: Shigenao MARUYAMA, Yuya ISEKI, Takuma KOGAWA, Takashi NONAKA, Yasushi HOSOKAWA, Takahiro OKABE, Yutaro TABATA, Tadashi MATSUDATE, Toshinori NAKAJIMA, Masaya HIGASHI, Manabu ORITO
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Publication number: 20230181135Abstract: A radiographic imaging device that obtains a radiographic image, includes a battery, a first hardware processor, and a storage. The battery drives the radiographic imaging device. The first hardware processor measures an amount of power remaining in the battery. The storage stores a first threshold and a second threshold of the amount of power remaining in the battery. The first threshold is used to allow photographing of a first photography mode. The second threshold is used to allow photographing of a second photography mode that consumes less power than the first photography mode.Type: ApplicationFiled: December 12, 2022Publication date: June 15, 2023Inventors: Tadashi MARUYAMA, Hiroshi UTSUNOMIYA
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Patent number: 8790907Abstract: A method for immobilizing living microorganisms includes a step (1) of disposing a solution containing microorganisms as an electrolyte on the surface of a substrate at least one portion of which is an electrode, and applying a constant potential to the electrode to cause at least a portion of the microorganisms to attach to the surface of the substrate. The constant potential in step (1) is greater than ?0.5 V but not greater than ?0.2 V (vs Ag/AgCl) or greater than +0.2 V but not greater than +0.4 V (vs Ag/AgCl). The electrolyte in step (1) does not contain a source of nutrition for the microorganisms.Type: GrantFiled: January 27, 2012Date of Patent: July 29, 2014Assignee: Japan Agency for Marine-Earth Science and TechnologyInventors: Sumihiro Koyama, Tadashi Maruyama, Chiaki Kato, Yuichi Nogi, Yuji Hatada, Yukari Ohta, Masaaki Konishi, Taishi Tsubouchi
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Publication number: 20130196404Abstract: A method for immobilizing living microorganisms includes a step (1) of disposing a solution containing microorganisms as an electrolyte on the surface of a substrate at least one portion of which is an electrode, and applying a constant potential to the electrode to cause at least a portion of the microorganisms to attach to the surface of the substrate. The constant potential in step (1) is greater than ?0.5 V but not greater than ?0.2 V (vs Ag/AgCl) or greater than +0.2 V but not greater than +0.4 V (vs Ag/AgCl). The electrolyte in step (1) does not contain a source of nutrition for the microorganisms.Type: ApplicationFiled: January 27, 2012Publication date: August 1, 2013Applicant: JAPAN AGENCY FOR MARINE-EARTH SCIENCE AND TECHNOLOGYInventors: Sumihiro Koyama, Tadashi Maruyama, Chiaki Kato, Yuichi Nogi, Yuji Hatada, Yukari Ohta, Masaaki Konishi, Taishi Tsubouchi
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Publication number: 20050130259Abstract: It is an object of the present invention to provide an expression vector, a host, a fused protein, a protein, a process for producing a fused protein, and a process for producing a protein, which can prevent formation of an unactive abnormal protein at production of a recombinant protein, and can produce a desired protein as a natural type, that is, a soluble type at a large amount and effectively. That is, the present invention is an expression vector, which comprises: (a) a first coding region encoding a polypeptide having molecular chaperone activity, and (b) a region having at least one restriction enzyme site in which a second coding region encoding a protein can be inserted.Type: ApplicationFiled: June 25, 2003Publication date: June 16, 2005Inventors: Akira Ideno, Tadashi Maruyama, Masahiro Furutani
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Patent number: 6504701Abstract: Control signals are input to the gates of a P-MOS transistor and an N-MOS transistor of a CMOS drive circuit from respective control signal generating sections. The CMOS drive circuit drives a piezoelectric member as a capacitive element and the piezoelectric element is used in an ink jet head. A substrate of the P-MOS transistor is provided with a voltage higher than a power supply of the CMOS drive circuit. A first potential difference is supplied between terminals of the piezoelectric element and thereafter, a second potential difference of a polarity opposite to the first potential difference is further supplied between the terminals. A discharge operation is inserted in a time period from the time when supply of the first potential difference is completed till the supply of the second difference gets started. The discharge operating time period is set to a proper value at which a desired operating speed, high reliability and low power consumption are achieved.Type: GrantFiled: September 27, 1999Date of Patent: January 7, 2003Assignees: Toshiba Tec Kabushiki Kaisha, Kabushiki Kaisha ToshibaInventors: Jun Takamura, Noboru Nitta, Shunichi Ono, Tadashi Maruyama
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Patent number: 6246740Abstract: A cylindrical thin-wall sleeve including an SiC fiber-reinforced SiC composite material (SiC/SiC), which has a porosity of 40% or less and a wall thickness of 5 mm or less.Type: GrantFiled: October 14, 1998Date of Patent: June 12, 2001Assignees: Japan Nuclear Cycle Development Institute, Nippon Carbon Co., Ltd.Inventors: Tadashi Maruyama, Shoji Onose, Shiro Mitsuno
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Patent number: 5946367Abstract: A neutron absorbing pin including at least, a neutron absorber, a thin-wall pipe surrounding the neutron absorber, and a cladding disposed at a distance from the thin-wall pipe. In the neutron absorbing pin, the difference between the coefficient of thermal expansion (.alpha.1) of the neutron absorber and the coefficient of thermal expansion (.alpha.2) of the thin-wall pipe has an absolute value of .vertline..alpha.2-.alpha.1.vertline..ltoreq.10.times.10.sup.-6 /K.Type: GrantFiled: December 11, 1998Date of Patent: August 31, 1999Assignee: Japan Nuclear Cycle Development InstituteInventors: Tadashi Maruyama, Shoji Onose
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Patent number: 5580658Abstract: A function ally gradient composite material containing copper and carbon as main components and having a predetermined shape, in which the composition ratio of the copper to the carbon in the material continuously varies in at least one predetermined direction. The material is manufactured, for example, by impregnating carbon felt with a resin and thermo-compressively molding the impregnated felt (step S101), carbonizing the resin by baking (step S102) to provide a preformed carbon material (step S104). Pyrolytic carbon is thereafter deposited in the preformed carbon material by the CVI method (step S105) to provide a carbon material having the bulk density varying in a predetermined direction (step S107). After the wettability of the carbon material against copper is improved by siliconization (step S108), pores of the carbon material are impregnated with copper (step S109) to obtain a functionally gradient composite material of copper and carbon.Type: GrantFiled: July 12, 1994Date of Patent: December 3, 1996Assignees: Doryokuro Kakunenryo Kaihatsu Jigyodan, Toyo Tanso Co., Ltd.Inventors: Tadashi Maruyama, Katuhide Nagaoka, Masaki Okada
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Patent number: 5341334Abstract: An input terminal inputs an input signal oscillating between a first power source voltage and second power source voltage according to a selected mode and a non-selected mode. An output terminal delivers a signal oscillating between the first and second power source voltages and a third power source voltage according to voltage conversion and non-voltage conversion. An N-channel E type transistor of a positive threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with the second power source voltage. An N-channel I type transistor of a neutral threshold voltage has a source electrode and a drain electrode connected between the input terminal and the output terminal and a gate electrode supplied with a control signal oscillating between the first power source voltage and the second power source voltage, the control signal determining whether or not a voltage conversion is made.Type: GrantFiled: September 1, 1993Date of Patent: August 23, 1994Assignee: Kabushiki Kaisha ToshibaInventor: Tadashi Maruyama
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Patent number: 5083761Abstract: A sheet storing apparatus wherein sheets ejected from a copying machine one after another are stacked in order, and the sheets are supplied to the copying machine again. The apparatus comprises a sheet storing unit wherein sheets are stored, a transporter for transporting sheets to the storing unit, a regulator for preventing sheets supported by a sheet support surface of the storing unit from moving back toward the entrance thereof, a pressure member for pressing each sheet transported to the unit against the support surface and a refeeder for feeding out the stored sheets one by one. Each time a sheet is transported to the unit, the pressure member presses the sheet, whereby the end of the sheet passes through the regulator to be put between the support surface and the regulator. Also, in feeding sheets out of the unit, the pressure member presses the sheet stack against the refeeder.Type: GrantFiled: August 30, 1989Date of Patent: January 28, 1992Assignee: Minolta Camera Kabushiki KaishaInventors: Akiyoshi Johdai, Keichi Kinoshita, Toshio Matsui, Takeshi Yoshikai, Tadashi Maruyama, Kazuhito Ozawa, Hiroki Yamashita
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Patent number: 5065361Abstract: A semiconductor memory integrated circuit is made up of a decoder, a memory matrix, and a decode output buffer selectively receiving a first or second power source voltage. The decode output buffer is provided between the decoder and the memory matrix, and includes an inverter circuit for inverting the output signal of the decoder, and a MOS transistor of a depletion mode, the gate of which is connected to the output terminal of the inverter, the first end of which is connected to a supply node of the first or second power source voltage, and the second end of which is connected to a power voltage supply node of the inverter circuit.Type: GrantFiled: December 5, 1989Date of Patent: November 12, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Yoshizawa, Tadashi Maruyama
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Patent number: 5058063Abstract: In a nonvolatile semiconductor memory system comprising a memory chip and a batttery for driving the memory chip, the memory chip includes a memory-cell matrix, a row decoder, a first level-shifting circuit for shifting the level of the output of the row decoder, a column-selecting circuit, a column decoder, a second level-shifting circuit for shifting the level of the output of the column decoder, a sense amplifier, a third level-shifting circuit for shifting the level of the data which is to be written into the memory-cell matrix, a voltage-booster circuit, a timer circuit, and an oscillator circuit. The nonvolatile semiconductor memory system operates stably when driven by a low voltage or by a voltage over a broad range.Type: GrantFiled: December 21, 1989Date of Patent: October 15, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Wada, Tadashi Maruyama, Yasoji Suzuki
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Patent number: 5058062Abstract: A nonvolatile memory device has a memory cell having its gate connected to a word line, its source connected to a ground potential and its drain connected to a power supply voltage via a bit line and a dummy cell having its gate connected to the word line, its source connected to the source potential and its drain connected to the power supply voltage via a dummy bit line. The bit line and the dummy bit line are connected to reset and set terminals of a sense amplifier circuit comprising a flip-flop circuit and a latch type of sense amplifier. The conductance of the dummy cell is made smaller than that of the memory cell so that the speed at which the potential on the bit line is lowered depends on the state of injection of electrons into the memory cell as compared with the speed at which the potential on the dummy bit line at a time of reading data.Type: GrantFiled: November 6, 1989Date of Patent: October 15, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Wada, Tadashi Maruyama, Toshimasa Nakamura
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Patent number: 5040147Abstract: A nonvolatile semiconductor memory is a programmable and erasable nonvolatile semiconductor memory including a semiconductor substrate of a first conductivity type, source and drain diffusion layers in the semiconductor substrate, and a channel region between the source and drain diffusion layers. A first insulation film is continuously on the channel region and the drain diffusion layer adjacent to the channel region, and a floating gate layer is on the first insulation film. Further, a second insulation film having a thin film portion which is thinner than the first insulation film is on the floating gate layer, and a control gate layer is on the second insulation film.Type: GrantFiled: March 16, 1990Date of Patent: August 13, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Makoto Yoshizawa, Katsuaki Mohri, Takeshi Nakashiro, Tadashi Maruyama
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Patent number: 5018108Abstract: A memory cell array includes a matrix array of a plurality of memory cells. These memory cells are non-volatile transistors. The memory cells which are arrayed in each row of the memory array, are coupled with a plurality of word lines. The word lines are selected by a row decoder made up of a plurality of partial decoders. In this case, a constant voltage output circuit, which is provided at the outputs of the partial decoders of the row decoder, outputs a constant voltage lower than a power source voltage to a corresponding word line of those word lines when the corresponding word line is selected by the outputs of the partial decoders.Type: GrantFiled: June 6, 1989Date of Patent: May 21, 1991Assignee: Kabushiki Kaisha ToshibaInventor: Tadashi Maruyama
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Patent number: 4992374Abstract: An improved mutant vaccinia virus providing a pock and plaque size on RK13 cells that is approximately the same as those of the Lister original, having a proliferation potency on YTV cells that is approximately the same as that of the Lister original, and having a neurovirulence, assessed by a recovery of an intrabrain virus, that is lower than that of the Lister original; and a process for the production thereof.Type: GrantFiled: July 30, 1987Date of Patent: February 12, 1991Assignees: Toa Nenryo Kogyo Kabushiki Kaisha, Chiba PrefectureInventors: Masanobu Sugimoto, Fukumi Nishimaki, Tadashi Maruyama, Keizaburo Miki, Michio Morita, Kazuyoshi Suzuki
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Patent number: 4970409Abstract: A voltage multiplier for a use in a non-volatile semiconductor memory and operated at a low operation voltage with a reduced area comprising a plurality of cascade-connected basic circuits.Type: GrantFiled: April 3, 1989Date of Patent: November 13, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Yukio Wada, Tadashi Maruyama
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Patent number: 4930105Abstract: A memory cell of a nonvolatile semiconductor memory device includes a P conductive type semiconductor substrate, first and second diffusion layers of an N conductivity type, formed in the substrate, a channel region formed in the surface region of the substrate, and which is located between the first and second diffusion layers, a floating gate electrode formed on the channel region, and a control gate electrode formed on the floating gate electrode. The memory cell further includes a third diffusion layer of the N conductivity type, and formed between the first layer and the channel region, the third layer having an impurity concentration lower than that of the first layer.Type: GrantFiled: April 7, 1988Date of Patent: May 29, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Osamu Matsumoto, Tadashi Maruyama, Hiroyoshi Murata, Isao Abe, Tomohisa Shigematsu, Kazuyoshi Shinada, Yasoji Suzuki, Ichiro Kobayashi