Patents by Inventor Tadashi Nakano

Tadashi Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5840821
    Abstract: A coating solution for forming an insulating film used in production of semiconductor devices includes siloxanes represented by a general formula:?SiR.sub.3 O.sub.1/2 !.sub.k ?SiR.sub.2 O.sub.2/2 !.sub.l ?SiRO.sub.3/2 !.sub.m ?SiO.sub.4/2 !.sub.nwhere each of k, l, m and n is an integer, R may be the same or different and represents at least one organic group, and a ratio of (3k+2l+m) to (k+l+m+n) is between about 0.8 and about 1.3. The present invention further relates to a method for preparing the coating solution, and a method for forming the insulating film using the coating solution, including the steps of coating the coating solution on a surface of a substrate of the semiconductor device to form a coated film, fluidizing the coated film at a temperature between about 150.degree. C. to about 300.degree. C. to planarize the surface of the substrate, and curing the fluidized coated film to form the insulating film.
    Type: Grant
    Filed: November 21, 1995
    Date of Patent: November 24, 1998
    Assignee: Kawasaki Steel Corporation
    Inventors: Tadashi Nakano, Makoto Shimura, Tomohiro Ohta
  • Patent number: 5627102
    Abstract: A metal interconnection is prepared by forming an underlying metal film of high melting point metal such as Ti and/or high melting point metal compound such as TiN layers above a semiconductor substrate, plasma etching the surface of the underlying metal film in a gas atmosphere containing chloride, and forming an interconnecting metal film such as Al, Cu, Au and Ag on the underlying metal film. Alternatively, a metal interconnection is prepared by forming an insulating film above a semiconductor substrate, forming connection holes in the insulating film, forming an underlying metal film such as TiN on the insulating film and the bottom and side wall of the connection holes by a CVD process under controlled conditions, and forming an interconnecting metal film such as Al on the underlying metal film. The TiN film has (111) preferential orientation and the aluminum film has (111) preferential orientation, smooth surface and effective coverage.
    Type: Grant
    Filed: December 8, 1995
    Date of Patent: May 6, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Hiroshi Shinriki, Takeshi Kaizuka, Nobuyuki Takeyasu, Tomohiro Ohta, Eiichi Kondoh, Hiroshi Yamamoto, Tomoharu Katagiri, Tadashi Nakano, Yumiko Kawano
  • Patent number: 5605867
    Abstract: In a method of manufacturing an insulating film of a semiconductor device by a chemical vapor deposition, a surface of a semiconductor wafer is treated with an organic compound such as ethanol and methanol, and then the semiconductor wafer is transported into a reaction chamber and an insulating film is deposited on the thus treated surface of the semiconductor wafer by a chemical vapor deposition using a raw material such as organic silicon compound. By treating the surface of the semiconductor wafer with the organic compound prior to the deposition, the filling capability and planarization of the insulating film are improved. Further the insulating film thus formed is free from voids and clacks, and an amount of water contained in the insulating film is very small. The treatment of the surface of the semiconductor wafer can be performed simply by spin coating, spaying, vapor exposing or dipping, so that the throughput can be improved.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: February 25, 1997
    Assignee: Kawasaki Steel Corporation
    Inventors: Nobuyoshi Sato, Tomohiro Ohta, Tadashi Nakano, Hiroshi Yamamoto
  • Patent number: 5532191
    Abstract: A method of planarizing an insuating film includes the steps of preparing a semiconductor substrate; treating an uneven surface of the substrate with an organic solvent; forming an insulating film on the thus-treated surface of the substrate by a chemical vapor deposition using an organic silicon compound as a raw material or depositing SOG, forming an etching stop film having a chemical mechanical polishing etching speed slower than that of the insulating film by depositing silicon oxide or silicon oxynitride by performing a chemical vapor deposition using an inorganic silicon compound as a raw material; and etching back at least a part of the insulating film formed on the uneven surface of the substrate by a chemical mechanical polishing process using the etching stop film.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: July 2, 1996
    Assignee: Kawasaki Steel Corporation
    Inventors: Tadashi Nakano, Nobuyoshi Sato, Tomohiro Ohta, Hiroshi Yamamoto
  • Patent number: 5506449
    Abstract: An interconnection structure for semiconductor integrated circuits and the method for manufacturing of the same are provided. The interconnection structure has a low electric resistance and a good electromigration resistance and can prevent the atoms in wire materials from diffusing into insulating films or substrates. More particularly, an insulating film 12 is formed on a silicon substrate 10, on which a tungsten 14 is formed. The tungsten film 14 is subjected to plasma irradiation on the surface thereof to form an amorphous W--N film 16. A copper wire pattern 20 is formed on the amorphous W--N film 16.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: April 9, 1996
    Assignee: Kawasaki Steel Corporation
    Inventors: Tadashi Nakano, Hideaki Ono
  • Patent number: 5300321
    Abstract: A process which is capable of depositing a titanium nitride film of a high quality at a high deposition rate by low temperature chemical vapor deposition is provided. The titanium nitride film is deposited using a gas source comprising a compound of the general formula:A.sub.n B.sub.m Tiwherein n and m are independently selected from integers of from 1 to 3 provided that sum of n and m is equal to or smaller than 4; A is selected from a cyclic hydrocarbon group and a nitrogen-containing heterocyclic group which is bonded to the titanium by .pi. electron; and B is an alkylamine derivative group containing a nitrogen atom which is directly bonded to the titanium. The film deposition process of the invention is highly useful in LSI fabrication.
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: April 5, 1994
    Assignee: Kawasaki Steel Corporation
    Inventors: Tadashi Nakano, Tomohiro Ohta
  • Patent number: 4438079
    Abstract: Arsenic anhydride of high purity is inexpensively manufactured from an arsenic sulfide-containing substance by first contacting the arsenic sulfide-containing substance with a copper sulfate-containing aqueous solution so as to provide an extract solution containing arsenious acid, the extract solution is subjected to aeration in the presence of copper ions such that the arsenious acid therein is mostly oxidized to arsenic acid, the thus provided treated solution is subjected to a weak reducing agent to cause crystals of arsenious anhydride to form, and these crystals are then recovered.
    Type: Grant
    Filed: March 26, 1982
    Date of Patent: March 20, 1984
    Assignee: Sumitomo Metal Mining Company Limited
    Inventors: Tadashi Nakano, Hiroyuki Tamura, Naoki Kubo
  • Patent number: 4361654
    Abstract: A porcelain enamel frit for sheet iron ground coat is disclosed, which contains neither fluorine nor fluorine compound, but has excellent firing property, and can be worked into sheet iron enamel having high gloss and adherence and low surface roughness. The frit consists of 100 parts of a main component and 7-42 parts of an auxiliary component, said main component consisting of 30-73 parts of SiO.sub.2 or a mixture of SiO.sub.2 and at least one of TiO.sub.2, ZrO.sub.2 and SnO.sub.2, 8-45 parts of B.sub.2 O.sub.3, and 8-41 parts of Na.sub.2 O or a mixture of Na.sub.2 O and at least one of Li.sub.2 O and K.sub.2 O, and said auxiliary component consisting of not more than 12 parts of Al.sub.2 O.sub.3, 1-22 parts of at least one of CaO, Bao, ZnO, MgO and SrO, from more than 0 part to 7 parts of MoO.sub.3 or a mixture of MoO.sub.3 and at least one of V.sub.2 O.sub.5, P.sub.2 O.sub.5 and Sb.sub.2 O.sub.3, and 0.5-10 parts of at least one of CoO, NiO, CuO, MnO.sub.2 and Fe.sub.2 O.sub.3.
    Type: Grant
    Filed: August 5, 1981
    Date of Patent: November 30, 1982
    Assignee: NGK Insulators, Ltd.
    Inventors: Akira Ohmura, Tadashi Nakano