Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

Abstract: Disclosed is a semiconductor computing circuit achievable with simple circuitry and capable of performing analog computations at high speed to compute an absolute-value voltage representing the difference between a first signal voltage and a second signal voltage.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: A semiconductor arithmetic circuit which compares the magnitudes of a plurality of data with each other in real time by using a simple circuit. The semiconductor arithmetic circuit containing one or more neuron MOS transistors each having a plurality of input gate electrodes has an inverter circuit group of a plurality of inverter circuit each of which is constituted of neuron MOS transistors and a means for applying a prescribed signal voltage to at least one first input gate of the inverter circuit.

Abstract: The present invention is intended to provide a semiconductor memory circuit that can store analog and many-valued data at high speed and with a high degree of accuracy.

Abstract: A function reconfigurable semiconductor device is provided. The function reconfigurable semiconductor device includes a plurality of function cells, each of the function cells being a basic unit which realizes a function; each of the function cells including a plurality of threshold elements; each of the threshold elements including means which stores a threshold value; and wherein a function which is realized by the function cell is determined by determining the threshold value in each of the threshold elements. In addition, the semiconductor device includes a nonvolatile memory which stores data for realizing the function in the function cells.

Abstract: A data transfer device for transferring plural asynchronous data processed and input/output at different rates includes a memory for storing data. The memory is shared between first through fourth data input/output circuits, and the data are input/output between the memory and the data input/output circuits. Each of the data input/output circuits is previously assigned a priority for access to the memory, and issues an access request at a predetermined time interval. An arbitration device receives the access requests from the data input/output circuits, and gives an access permission to the data input/output circuits issuing the access requests in the descending order of the priorities. Accordingly, the asynchronous data can be real time transferred by using a small circuit scale.

Abstract: A semiconductor device capable of executing size comparison operations on a plurality of data at high speed and in real time and using simple circuitry. An inverter circuit group is used containing a plurality of inverter circuits constructed using neuron MOS transistors. Predetermined signal voltages are applied from the exterior to the first input gates of the inverter circuits, and the output signals of all inverters contained in the inverter circuit group are inputted into a first logical arithmetic circuit and a second logical arithmetic circuit, and the output signal of the first logical arithmetic circuit is inputted into a third logical arithmetic circuit controlled by the output signal of the second logical arithmetic circuit, and the output of the third logical arithmetic circuit is fed back to the second input gates of the inverter circuits contained in the inverter circuit group.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: The problem of increase in jitter amounts against increase in delay amounts is solved by a circuit wherein a signal input terminal is connected through a first capacitor to an input terminal of a sense amplifier, a control input terminal is connected through a second capacitor to the input terminal of the sense amplifier, and a common connection point between the input terminal of the sense amplifier and the first and second capacitors is a floating node, and wherein a signal applied through the signal input terminal to the input terminal of the sense amplifier is vertically shifted by a control signal applied to the control input terminal, at least, near a determination threshold of the sense amplifier, thereby controlling a delay amount of an output.

Abstract: In order to solve the problem of increase in circuit scale and increase in power consumption due to use of a DA converter, a semiconductor integrated circuit comprises a signal amplifier 2, 10 capable of switching of a gain to 1 or 2, an arithmetic processor 7, 9 for performing a subtraction process of a reference voltage from an input signal to output a result thereof or for outputting the input signal without performing the subtraction process, a switch 8 whose one switch terminal is connected to a signal input terminal, whose other switch terminal is connected to an output side of sample hold circuits 5, 6, and whose common terminal is connected to an input side of the arithmetic processor, a comparator 3 for comparing an output from the signal amplifier with the reference voltage to binarize the output, and a switch 11 for connecting an output side of the signal amplifier to an input side of the sample hold circuits, wherein the arithmetic processor carries out a changeover between the operation of perfor

Abstract: A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state.

Abstract: Vacuum processing equipment capable of preventing particles from sticking to objects to be processed in vacuum vessels. The vacuum equipment comprises a series of vacuum vessels separated by doors, and the pressure in the vessels are reducible respectively. The vessels are so configured that objects to be processed are movable among them, and there is provided light projection means for projecting ultra rays on gases introduced to at least of the vessels.

Abstract: In order to prevent an output offset voltage from occurring because of a relative difference of threshold voltage Vth between NMOS and PMOS in transmission of dc voltage, a semiconductor integrated circuit is constructed in a circuit configuration comprising a first depletion-mode N-channel MOS transistor and a first depletion-mode P-channel MOS transistor, a gate of each transistor being connected to an input terminal and a source of each transistor being connected to an output terminal, a second depletion-mode N-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transistor being connected both to a lower-voltage-side power supply, and a second depletion-mode P-channel MOS transistor having W/L equal to that of the first depletion-mode P-channel MOS transistor, a drain of the transistor being connected to the output terminal and a gate and a source of the transist

Abstract: To retrieve analog signals at high precision by a maximum or minimum position detection parallel signal processing circuit, a plurality of circuit units in each of which a gate of a transistor is connected to a signal input terminal through first capacitive means, a common connecting point of the gate and the first capacitive means is connected to one terminal side of second capacitive means, and control means, for fluctuating a voltage on the other terminal side of the second capacitive means so as to further increase or decrease a drain current in correspondence to an increase or decrease in the drain current is connected between the drain and the other terminal side of the second capacitive means are provided, a source of each transistor of the plurality of circuit units is commonly connected and is connected to a constant current source, and the maximum or minimum voltage position detection with respect to a signal voltage which is applied to each signal input terminal is performed by a voltage on the oth

Abstract: The real time compression of moving images employing vector quantization is realized using simple hardware and with an optimal compression ratio with respect to the communication line capacity employed.

Abstract: For raising the accuracy of analog multiplication, a gate-drain (G-D) connection point of transistor (Tr) whose gate-drain (G-D) are shorted and whose source is connected to ground potential is connected to a source of second Tr whose G-D are shorted, a first input signal current source is connected to a G-D connection point of the second Tr, a G-D connection point of third Tr whose G-D are shorted and whose source is connected to the ground potential is connected to a source of fourth Tr whose G-D are shorted, a second input signal current source is connected to a G-D connection point of the fourth Tr, the G-D connection points of the second and fourth Tr's are connected to first and second capacitors respectively, outputs of the first and second capacitors are connected to each other and to a gate of fifth Tr to form a floating point, a source of the fifth Tr is connected to the ground potential, and a drain current of the fifth Tr is an operation output.

Abstract: A gate valve for a thin film forming apparatus. The gate valve includes two adjoining low-pressure chambers and a wall separating the two chambers. The wall includes an aperture and a thin plate for covering the aperture. The thin plate is movable in a direction substantially parallel to the plate surface. The gate valve further includes a voltage supply for applying a direct current between the thin plate and the wall.

Abstract: A semiconductor circuit assembly is capable of accurately storing a plurality of analog or multi-valued data using circuitry having a small surface area. The circuit assembly includes a first circuit provided in the form of a target memory cell device comprising memory cells which conduct the writing and storage of analog signals. The first circuit has output terminals for outputting stored values to the exterior as voltage signals. Mechanisms supply at least two index voltages. A second circuit performs the function of halting the writing of the analog signals when the output signal at the first circuit output terminals reaches a value representing a desired voltage plus the difference between the two index voltages.

Abstract: A thin film transistor device with its leakage current being controlled is provided. With such a thin film transistor device incorporated, a liquid crystal display apparatus presents a high-contrast image at a reduced power consumption. The thin film transistor is formed on an insulating substrate. The gate electrode of the transistor is electrically floating gate electrode, which is capacitance coupled to one or more input electrodes. The liquid crystal display apparatus incorporates the thin film transistor in its switching element and/or driving circuit.