Patents by Inventor Tadashi Yamamoto

Tadashi Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180354265
    Abstract: A thermal print head includes: a substrate having an obverse surface; a plurality of heat generators arranged on the substrate in a main scanning direction; and a wiring layer provided on the substrate and constituting an energization path to the heat generators. The substrate has a protrusion protruding from the obverse surface and extending in the main scanning direction. The protrusion has a top portion having the largest distance from the obverse surface, and an inclined portion connected to the top portion in a sub-scanning direction. The inclined portion is inclined relative to the obverse surface at a predetermined angle. Each of the plurality of heat generators extends across a boundary between the top portion and the inclined portion. Each of the heat generators is formed on at least a part of the top portion and at least a part of the inclined portion in the sub-scanning direction.
    Type: Application
    Filed: May 31, 2018
    Publication date: December 13, 2018
    Inventors: Yoichi AOKI, Tadashi YAMAMOTO, Masatoshi NAKANISHI
  • Patent number: 10131089
    Abstract: Provided is a process for producing an automotive glass with a member in a highly efficient and space-saving manner.
    Type: Grant
    Filed: August 18, 2015
    Date of Patent: November 20, 2018
    Assignees: NAOMOTO CORPORATION, HORI GLASS CO., LTD.
    Inventors: Tadashi Yamamoto, Toshihiro Oyama, Isao Kurihashi, Teruki Umezawa, Jun Kurimoto, Hiroyuki Harada
  • Publication number: 20180273063
    Abstract: A train-position detection device (1) includes: a radio-wave's angle-of-arrival calculator (14) configured to calculate an angle of arrival of a radio wave on the basis of a reception signal received by an array antenna (11) and a receiver (12); a position acquisition unit (13) for a ground-based wireless communication apparatus, configured to acquire information on an installation position of a ground-based wireless communication apparatus (30) from the reception signal; a train-position calculator (15) configured to calculate a train position on the basis of a movement distance of a train (40); a correction-amount-to-train-position calculator (16b) configured to calculate a train-position correction amount, by using the radio wave's angle of arrival calculated by the radio-wave's angle-of-arrival calculator (14), the installation position of the ground-based wireless communication apparatus (30) acquired by the position acquisition unit (13) for a ground-based wireless communication apparatus, and the train
    Type: Application
    Filed: October 20, 2015
    Publication date: September 27, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Wataru TSUJITA, Seiya NAGASHIMA, Tadashi YAMAMOTO, Kazuhiro TAHARA, Kenji KATAOKA
  • Publication number: 20180236568
    Abstract: A drill has a thinning rake face formed in the front end. An intersection ridgeline between the thinning rake face and the tip flank face is the thinning edge. On the opposite side of the rotation direction, the first and second thinning wall surfaces (6b, 6c) and are formed. Viewed from the front, an intersection angle between the thinning edge (4a) and the first thinning ridgeline is larger than 95°. The second thinning ridgeline (L2) is bent to the opposite side of the rotation direction. The thinning edge and the first thinning ridgeline are connected via a concave curve line. The first and second thinning wall surfaces are connected via a concave surface, and a curvature radius of the concave curve line is smaller than a curvature radius of the concave surface.
    Type: Application
    Filed: August 29, 2016
    Publication date: August 23, 2018
    Applicants: MITSUBISHI MATERIALS CORPORATION, MITSUBISHI MATERIALS CORPORATION
    Inventors: Tadashi Yamamoto, Kazuya Yanagida, Yuya Tsurumaki
  • Publication number: 20180203127
    Abstract: A test signal generator generates a first test signal. A test signal transmitter transmits the first test signal. An RF receiver unit receives the first test signal and a first satellite signal through a receiving antenna, and generates a second test signal and a second satellite signal, respectively. Each of first and second demodulators calculates a correlation value between the second satellite signal and the spreading code to acquire a satellite. A first failure detector unit compares a signal intensity of the second test signal with a threshold to generate a first failure detection signal. A second failure detector compares the satellites acquired by the first and second demodulator to generate a second failure detection signal. A state determiner determines whether and where a failure exists, using the first and second failure detection signals.
    Type: Application
    Filed: May 10, 2016
    Publication date: July 19, 2018
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Tomoaki TAKEWA, Wataru TSUJITA, Yoshitsugu SAWA, Kenji KATAOKA, Tadashi YAMAMOTO, Seiya NAGASHIMA
  • Publication number: 20170274461
    Abstract: A drill comprising: a drill main body; a chip discharge flute; and a tip cutting edge. The tip cutting edge includes: a first tip cutting edge which extends toward the axially posterior end as it goes toward the outside in a radial direction; and a second tip cutting edge which is disposed outside the first tip cutting edge in the radial direction. The second tip cutting edge extends toward the tip in the axis direction as it goes toward the outside in the radial direction or extends to be perpendicular to the axis. The radially inner end of the second tip cutting edge is disposed on the axially posterior end with respect to the radially outer end of the first tip cutting edge. The radially outer end of the second tip cutting edge is disposed on a virtual extension line of the first tip cutting edge.
    Type: Application
    Filed: September 28, 2015
    Publication date: September 28, 2017
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventors: Masayuki Mabuchi, Koichiro Naruke, Souhei Takahashi, Takahiro Hibi, Tadashi Yamamoto, Kazuya Yanagida
  • Patent number: 9744774
    Abstract: The present invention provides a thermal print head and a thermal printer that can deliver improved printing quality. The thermal print head includes a main substrate with a main surface, heating elements arranged along a main scanning direction, and a protection layer that covers the heating elements. A belt-shaped heating glaze layer is between the main surface and the heating elements, extends along the main scanning direction, and bulges towards the direction where the main surface faces. The surface shape of the protection layer has an equivalent radius of curvature Re between 6200 ?m and 15000 ?m. The equivalent radius of curvature Re is calculated by Hq and Wq. Hq is ¼ of the maximum height Hm of the bulging portion of the protection layer including the heating glaze layer. Wq is the width of the bulging portion along a sub-scanning direction, measured at a height equal to Hm minus Hq.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: August 29, 2017
    Assignee: ROHM CO., LTD.
    Inventors: Koji Nishi, Tadashi Yamamoto
  • Publication number: 20170232663
    Abstract: Provided is a process for producing an automotive glass with a member in a highly efficient and space-saving manner.
    Type: Application
    Filed: August 18, 2015
    Publication date: August 17, 2017
    Applicants: NAOMOTO CORPORATION, HORI GLASS CO., LTD.
    Inventors: Tadashi YAMAMOTO, Toshihiro OYAMA, Isao KURIHASHI, Teruki UMEZAWA, Jun KURIMOTO, Hiroyuki HARADA
  • Publication number: 20170182793
    Abstract: The present invention provides a thermal print head and a thermal printer that can deliver improved printing quality. The thermal print head includes a main substrate with a main surface, heating elements arranged along a main scanning direction, and a protection layer that covers the heating elements. A belt-shaped heating glaze layer is between the main surface and the heating elements, extends along the main scanning direction, and bulges towards the direction where the main surface faces. The surface shape of the protection layer has an equivalent radius of curvature Re between 6200 ?m and 15000 ?m. The equivalent radius of curvature Re is calculated by Hq and Wq. Hq is ¼ of the maximum height Hm of the bulging portion of the protection layer including the heating glaze layer. Wq is the width of the bulging portion along a sub-scanning direction, measured at a height equal to Hm minus Hq.
    Type: Application
    Filed: December 20, 2016
    Publication date: June 29, 2017
    Inventors: Koji NISHI, Tadashi YAMAMOTO
  • Publication number: 20170175263
    Abstract: A method of reducing static charge of a plastic container is provided. The method includes providing a PECVD coating of SiCOH, SiOx or SiOH to an external support surface of the container. The PECVD coating reduces static charge of the container compared to a reference container that is essentially identical to the container except that the reference container is uncoated.
    Type: Application
    Filed: March 24, 2015
    Publication date: June 22, 2017
    Inventors: Tadashi Yamamoto, Christopher Weikart, John T. Felts, John Berggren
  • Patent number: 9558844
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Grant
    Filed: November 25, 2014
    Date of Patent: January 31, 2017
    Assignee: Micron Technology, Inc.
    Inventor: Tadashi Yamamoto
  • Patent number: 9466348
    Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: October 11, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Jacob Robert Anderson, Kang-Yong Kim, Tadashi Yamamoto, Zer Liang, Huy Vo
  • Patent number: 9423121
    Abstract: Provided is a superheated-steam generator device, in which the steam-loop-back structure of a steam-heating pipe is simplified and heaters can be individually attached to or removed from the device. The device includes a first disc, a second disc, a third disc, a fourth disc, and a fifth disc; multiple through-holes respectively are provided to the first disc, the third disc, and the fourth disc; at least one long through-hole and one through-hole are provided to the second disc; multiple steam-heating pipes are attached to the through-holes of the third disc and to the through-holes of the fourth disc; loop-back grooves and one through-hole are provided to the fifth disc; heaters that have spiral fins are attached into the through-hole of the first disc so as to cover the through-hole of the first disc; a steam-supply pipe; and a steam-discharge pipe.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: August 23, 2016
    Assignee: MASDAC CO., LTD.
    Inventors: Fumiharu Masuda, Shuichi Sanda, Takeshi Hayano, Tadashi Yamamoto, Masanori Arakawa
  • Patent number: 9216460
    Abstract: A coolant-hole equipped drill includes a drill main body, a cutting edge portion which has a tip flank, a chip discharging groove provided with a front groove wall surface and a rear groove wall surface, a cutting edge formed at a ridge line portion where the front groove wall surface and the tip flank intersect with each other, a land portion formed between the chip discharging grooves adjacent to each other in the rotating direction, and a coolant hole drilled at the land portion and opened at the tip flank. The coolant hole includes a front hole wall surface, a rear hole wall surface, and an outer-circumference hole wall surface.
    Type: Grant
    Filed: June 15, 2010
    Date of Patent: December 22, 2015
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Matsuda, Hiroyuki Higashi, Koichiro Naruke, Tadashi Yamamoto, Kazuya Yanagida
  • Patent number: 9147989
    Abstract: A femtosecond laser based laser processing system having a femtosecond laser, frequency conversion optics, beam manipulation optics, target motion control, processing chamber, diagnostic systems and system control modules. The femtosecond laser based laser processing system allows for the utilization of the unique heat control in micromachining, and the system has greater output beam stability, continuously variable repetition rate and unique temporal beam shaping capabilities.
    Type: Grant
    Filed: December 9, 2013
    Date of Patent: September 29, 2015
    Assignee: IMRA AMERICA, INC.
    Inventors: Lawrence Shah, James M. Bovatsek, Alan Y. Arai, Tadashi Yamamoto, Rajesh S. Patel, Donald J. Harter
  • Publication number: 20150092503
    Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. Chip enable circuits having control logic are configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 2, 2015
    Inventors: JACOB ROBERT ANDERSON, KANG-YONG KIM, TADASHI YAMAMOTO, ZER LIANG, HUY VO
  • Publication number: 20150085968
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Application
    Filed: November 25, 2014
    Publication date: March 26, 2015
    Inventor: Tadashi Yamamoto
  • Patent number: 8913447
    Abstract: Memories containing command decoder, chip enable, and signal truncation circuits are disclosed. One such command decoder circuit may include command decoder logic configured to receive command signals and output a decoded command to an interconnect bus responsive to a chip select signal having an active state. Decoder circuits may also prevent coupling commands to the interconnect bus based on the receipt of chip select signals having inactive states. The memory further may include chip enable circuits having control logic configured to receive chip select signals and provide the chip select signals to an interconnect bus responsive to receiving a valid command. Chip enable circuits may also prevent coupling chip select signals to the interconnect bus from chip enable signals based on the receipt of invalid command signals. Signal truncation circuits may be used to shorten and/or shift chip select signals to increase timing margins and improve the reliability of command execution by memories.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: December 16, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Jacob Robert Anderson, Kang-Yong Kim, Tadashi Yamamoto, Zer Liang, Huy Vo
  • Patent number: 8902680
    Abstract: Various embodiments comprise apparatuses to assign unique device identifier values to addressable devices in a stacked package. In one embodiment, an apparatus is disclosed including a stacked package with at least two addressable devices. Each of the addressable devices includes data input and switch path circuitry, a shift register coupled to the data input and switch path circuitry, and a single through-substrate via (TSV) through which the unique device identifier values can be assigned. The single TSV is coupled to the data input and switch path circuitry and between adjacent ones of the at least two addressable devices. Additional apparatuses, systems, and methods are described.
    Type: Grant
    Filed: January 23, 2013
    Date of Patent: December 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Tadashi Yamamoto
  • Publication number: 20140301723
    Abstract: Provided is a superheated-steam generator device, in which the steam-loop-back structure of a steam-heating pipe is simplified and heaters can be individually attached to or removed from the device. The device includes a first disc, a second disc, a third disc, a fourth disc, and a fifth disc; multiple through-holes respectively are provided to the first disc, the third disc, and the fourth disc; at least one long through-hole and one through-hole are provided to the second disc; multiple steam-heating pipes are attached to the through-holes of the third disc and to the through-holes of the fourth disc; loop-back grooves and one through-hole are provided to the fifth disc; heaters that have spiral fins are attached into the through-hole of the first disc so as to cover the through-hole of the first disc; a steam-supply pipe; and a steam-discharge pipe.
    Type: Application
    Filed: November 20, 2013
    Publication date: October 9, 2014
    Applicant: MASDAC CO., LTD.
    Inventors: Fumiharu Masuda, Shuichi Sanda, Takeshi Hayano, Tadashi Yamamoto, Masanori Arakawa