Patents by Inventor Tae-Hun Kim

Tae-Hun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10651195
    Abstract: A three-dimensional semiconductor memory device includes an electrode structure including gate electrodes and insulating layers, which are alternately stacked on a substrate, a semiconductor pattern extending in a first direction substantially perpendicular to a top surface of the substrate and penetrating the electrode structure, a tunnel insulating layer disposed between the semiconductor pattern and the electrode structure, a blocking insulating layer disposed between the tunnel insulating layer and the electrode structure, and a charge storing layer disposed between the blocking insulating layer and the tunnel insulating layer. The charge storing layer includes a plurality of first charge trap layers having a first energy band gap, and a second charge trap layer having a second energy band gap larger than the first energy band gap. The first charge trap layers are embedded in the second charge trap layer between the gate electrodes and the semiconductor pattern.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwan Lee, Yongseok Kim, Byoung-Taek Kim, Tae Hun Kim, Dongkyun Seo, Junhee Lim
  • Publication number: 20200144285
    Abstract: A vertical semiconductor device includes a plurality of channel connection patterns, a lower insulation layer, a supporting layer, a stacked structure, and a channel structure. The channel connection patterns, on which the lower insulation layer is formed, contact a substrate. The supporting layer is formed on the lower insulation layer to be spaced apart from the channel connection patterns, and includes polysilicon doped with impurities. The stacked structure is formed on the supporting layer, and includes insulation layers and gate electrodes to form a memory cell string. The channel structure passes through the stacked structure, the supporting layer and the lower insulation layer, and includes a charge storage structure and a channel which contacts the channel connection patterns. The charge storage structure and the channel face the gate electrodes and the supporting layer. The supporting layer serves as a gate of a gate induced drain leakage (GIDL) transistor.
    Type: Application
    Filed: May 2, 2019
    Publication date: May 7, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-Yong LEE, Tae-Hun KIM, Min-Kyung BAE, Myung-Hun WOO
  • Publication number: 20200135699
    Abstract: A semiconductor package includes a base structure having a base pad, a first semiconductor chip on the base structure, and having a first connection pad bonded to the base pad, a first bonding structure including an base insulation layer of a base structure and a first lower insulation layer of the first semiconductor chip bonded to the base insulation layer, a second semiconductor chip on the first semiconductor chip, and having a second connection pad connected to the first through-electrode, and a second bonding structure including a first upper insulation layer of the first semiconductor chip, and a second lower insulation layer of the second semiconductor chip bonded to the first upper insulation layer, and the first upper insulation layer has a dummy insulation portion extending onto the base structure around the first semiconductor chip.
    Type: Application
    Filed: October 1, 2019
    Publication date: April 30, 2020
    Inventors: Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG, Tae Hun KIM, Hyuek Jae LEE
  • Publication number: 20200135636
    Abstract: A semiconductor package is provided. The semiconductor package includes a lower structure including an upper insulating layer and an upper pad; and a semiconductor chip provided on the lower structure and comprising a lower insulating layer and a lower pad. The lower insulating layer is in contact with and coupled to the upper insulating layer and the lower pad is in contact with and coupled to the upper pad, and a lateral side of the semiconductor chip extends between an upper side and a lower side of the semiconductor chip and comprises a recessed portion.
    Type: Application
    Filed: June 25, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae LEE, Ji Hoon KIM, Tae Hun KIM, Ji Seok HONG, Ji Hwan HWANG
  • Publication number: 20200135594
    Abstract: A semiconductor package includes a base including a first bonding structure; and a first semiconductor chip, including a second bonding structure, the second bonding structure being coupled to the first bonding structure of the base, wherein the first bonding structure includes: a test pad; a first pad being electrically connected to the test pad; and a first insulating layer, wherein the second bonding structure includes: a second pad being electrically connected to the first pad; and a second insulating layer being in contact with the first insulating layer, and wherein at least a portion of the test pad is in contact with the second insulating layer.
    Type: Application
    Filed: July 11, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyuek Jae LEE, Tae Hun KIM, Ji Hwan HWANG, Ji Hoon KIM, Ji Seok HONG
  • Publication number: 20200135683
    Abstract: A semiconductor package includes a first semiconductor chip including a body portion, a first bonding layer disposed on a first surface of the body portion, and through vias passing through at least a portion of the body portion; and a first redistribution portion disposed in the first semiconductor chip to be connected to the first semiconductor chip through the first bonding layer, the first redistribution portion including first redistribution layers electrically connected to the first semiconductor chip, a first wiring insulating layer disposed between the first redistribution layers, and a second bonding layer connected to the first bonding layer. The first bonding layer and the second bonding layer include first and metal pads disposed to correspond to each other and bonded to each other, respectively, and a first insulating layer and a second bonding insulating layer surrounding the first metal pads and the second metal pads, respectively.
    Type: Application
    Filed: July 15, 2019
    Publication date: April 30, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun Chul Kim, Tae Hun Kim, Ji Hwan Hwang
  • Publication number: 20200135698
    Abstract: A die stack structure may include a base die having base contact pads insulated by a base protection patterns and a flat side surface, a die stack bonded to the base die and having a plurality of component dies on the base die such that each of the component dies includes component contact pads insulated by a corresponding component protection pattern, and a residual mold unevenly arranged on a side surface of the die stack such that the component dies are attached to each other by the residual mold.
    Type: Application
    Filed: August 6, 2019
    Publication date: April 30, 2020
    Inventors: Ji-Seok HONG, Ji-Hoon KIM, Tae-Hun KIM, Hyuek-Jae LEE, Ji-Hwan HWANG
  • Publication number: 20200135684
    Abstract: A semiconductor package includes a first semiconductor chip including a first bonding layer, on one surface, and a chip structure stacked on the first semiconductor chip and including a second bonding layer on a surface facing the first semiconductor chip and a plurality of second semiconductor chips. The plurality of second semiconductor chips includes a chip area and a scribe area outside of the chip area, respectively, the plurality of second semiconductor chips being connected to each other by the scribe area in the chip structure. The first and second bonding layers include first and second metal pads disposed to correspond to each other and bonded to each other, respectively and first and second bonding insulating layers surrounding the first and second metal pads, respectively.
    Type: Application
    Filed: July 19, 2019
    Publication date: April 30, 2020
    Inventors: Sun Chul KIM, Tae Hun KIM, Ji Hwan HWANG
  • Patent number: 10636808
    Abstract: A vertical memory device and method of manufacture thereof are provided. The vertical memory device includes gate electrode layers stacked on a substrate; a channel layer penetrating through the gate electrode layers; and a first epitaxial layer in contact with a lower portion of the channel layer and including a region having a diameter smaller than an external diameter of the channel layer.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung Hwan Lee, Yong Seok Kim, Tae Hun Kim, Byoung Taek Kim, Jun Hee Lim
  • Patent number: 10622520
    Abstract: A semiconductor light emitting device includes a light-emitting structure including a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer, a first transparent electrode layer on the second conductivity-type semiconductor layer, a first insulating layer on the first transparent electrode layer, the first insulating layer including a plurality of through-holes, a reflective electrode layer on the first insulating layer and connected to the first transparent electrode layer through the plurality of through-holes, and a transparent protection layer covering upper and side surfaces of the reflective electrode layer, the transparent protection layer being on a portion of the first insulating layer.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Jung Hwan Kil, Tae Hun Kim, Hwa Ryong Song, Jae In Sim
  • Publication number: 20200097043
    Abstract: Provided is a display device including a display panel configured to display an image forward. The display device includes a top chassis arranged on the front of the display panel; a bottom chassis arranged on the back of the display panel; a rear cover covering the back of the bottom chassis; and a stand unit including a stand provided to support the display device, a locking device provided to lock the stand to be pulled in between the bottom chassis and the rear cover, and a rotation guide provided to rotate at least a portion of the stand, wherein the rear cover includes a through hole formed for the stand to move vertically, and the stand is locked in the locking device and pulled in between the bottom chassis and the rear cover, or the stand is pulled out of the display device through the through hole.
    Type: Application
    Filed: May 29, 2019
    Publication date: March 26, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hee Bong KIM, Tae Hun KIM, Yong Gu DO, Gil Jae LEE, Pil Kwon JUNG
  • Publication number: 20200075767
    Abstract: The present invention disclosures an oxide semiconductor transistor and a method of fabricating the same. The oxide semiconductor transistor according to an embodiment of the present invention includes a first gate electrode formed on a substrate; a first gate insulating film formed using a solution process on the first gate electrode; a source electrode and a drain electrode separately formed on one surface of the first gate insulating film; an oxide semiconductor film formed using a solution process on the first gate insulating film and the source and drain electrodes; a second gate insulating film formed using a solution process on the oxide semiconductor film; pixel electrodes separately formed on one surface of the second gate insulating film and electrically connected to the source and drain electrodes, respectively; and a second gate electrode formed on the second gate insulating film.
    Type: Application
    Filed: September 13, 2017
    Publication date: March 5, 2020
    Applicant: UNIVERSITY-INDUSTRY COOPERATION GROUP OF KYUNG HEE UNIVERSITY
    Inventors: Jin JANG, Tae Hun KIM
  • Patent number: 10573786
    Abstract: A semiconductor light emitting device includes: a light emitting structure having a first conductivity-type semiconductor layer, an active layer, and a second conductivity-type semiconductor layer stacked therein along a stacking direction, a transparent electrode layer on the second conductivity-type semiconductor layer and divided into first and second regions, the transparent electrode layer having a plurality of first through-holes disposed in the first region, an insulating reflective layer covering the transparent electrode layer and having a plurality of second through-holes in a region overlapping the second region along the stacking direction, and a reflective electrode layer on the region of the insulating reflective layer and connected to the transparent electrode layer through the plurality of second through-holes.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: February 25, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Tae Hun Kim, Jae In Sim
  • Publication number: 20200054656
    Abstract: Provided is a pharmaceutical composition comprising an antidiabetic agent and an antihypertensive agent as active ingredients.
    Type: Application
    Filed: August 31, 2018
    Publication date: February 20, 2020
    Applicants: AUTOTELIC BIO INC., AUTOTELIC BIO INC.
    Inventor: Tae Hun KIM
  • Patent number: 10565050
    Abstract: According to an aspect of inventive concepts, there is provided a memory controller configured to control a memory device including a plurality of memory pages, the memory controller including an error correction code (ECC) region manager configured to manage the plurality of memory pages by dividing the plurality of memory pages into ECC enable regions and ECC disable regions, and an ECC engine configured to perform an ECC operation on data included in the ECC enable regions.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: February 18, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Tae-hun Kim, Yong-sang Yu, Man-hwee Jo, Min-young Joe, Ji-woong Kim, Nak-hee Seong
  • Publication number: 20200053891
    Abstract: A display device is disclosed. The display device comprises: a display unit for displaying an image; a support for supporting the display unit; and a rotating unit for rotatably connecting the display unit to one surface part of the support; wherein the rotating unit rotates the display unit after tilting the same in a first tilting direction with respect to the one surface part of the support.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 13, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-hun KIM, Chul-yong CHO, Se-jin YOON
  • Patent number: 10541350
    Abstract: A light-emitting device includes a light-emitting chip having a first surface and a second surface. A first light reflection pattern is formed on the second surface. A plurality of terminals are disposed to be connected to the light-emitting chip by passing through the first light reflection pattern. A second light reflection pattern is formed on side surfaces of the light-emitting chip and the first light reflection pattern. A light-transmitting pattern is formed between the light-emitting chip and the second light reflection pattern and extends between the first light reflection pattern and the second light reflection pattern. A wavelength conversion layer is formed on the first surface of the light-emitting chip.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: January 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju Heon Yoon, Jae In Sim, Tae Hun Kim, Gi Bum Kim
  • Publication number: 20200020717
    Abstract: A three-dimensional (3D) semiconductor memory device may include a stack structure including gate electrodes sequentially stacked on a substrate, and a vertical channel penetrating the stack structure. The gate electrodes may include a ground selection gate electrode, a cell gate electrode, a string selection gate electrode, and an erase gate electrode, which are sequentially stacked on the substrate.
    Type: Application
    Filed: February 1, 2019
    Publication date: January 16, 2020
    Inventors: BONGYONG LEE, TAE HUN KIM, Minkyung BAE
  • Publication number: 20190384441
    Abstract: A touch input device capable of detecting a pressure of a touch on a touch surface may be provided. The touch input device includes: a display panel; a substrate disposed under the display panel; and a pressure sensing unit. The pressure sensing unit includes a pressure sensor and a reference pressure sensor. When a pressure is applied to the touch surface, the display panel is bent. Electrical characteristics detected at the pressure sensor change by the bending of the display panel. A magnitude of the pressure applied to the touch surface is calculated based on a difference between a reference electrical characteristic calculated from electrical characteristics detected at the reference pressure sensor and the detected electrical characteristic calculated from the electrical characteristics detected at the pressure sensor.
    Type: Application
    Filed: November 24, 2016
    Publication date: December 19, 2019
    Inventors: Bong Jin Seo, Bon Kee Kim, Myung Jun Jin, Tae Hun Kim
  • Patent number: 10505073
    Abstract: A semiconductor light emitting device including a floating conductive pattern is provided. The semiconductor light emitting device includes a first semiconductor layer including a recessed region and a protruding region, an active layer and a second semiconductor layer disposed on the protruding region, a contact structure disposed on the second semiconductor layer, a lower insulating pattern covering the first semiconductor layer and the contact structure, and having first and second openings, a first conductive pattern disposed on the lower insulating pattern and extending into the first opening, a second conductive pattern disposed on the lower insulating pattern and extending into the second opening, and a floating conductive pattern disposed on the lower insulating pattern. The first and second conductive patterns and the floating conductive pattern have the same thickness on the same plane.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Young Kyu Sung, Jae Yoon Kim, Tae Hun Kim, Gam Han Yong, Dong Yeoul Lee, Su Yeol Lee