Patents by Inventor Taeg Ki Lim

Taeg Ki Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8987056
    Abstract: A method of manufacture of a semiconductor package system includes: attaching an internal stacking module die to a surface of an internal stacking module substrate having an internal stacking module bonding pad along an edge of an opposite surface thereof; and attaching a support carrier to support the internal stacking module substrate by two edges thereof with the internal stacking module bonding pad exposed.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: March 24, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Jong-Woo Ha, Sung Yoon Lee, Taeg Ki Lim
  • Patent number: 8659175
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Grant
    Filed: June 12, 2007
    Date of Patent: February 25, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim
  • Patent number: 8618653
    Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.
    Type: Grant
    Filed: January 30, 2008
    Date of Patent: December 31, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Taeg Ki Lim, Sungmin Song
  • Patent number: 8409921
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: April 2, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Heap Hoe Kuan, Hamid Eslampour, DaeSik Choi, Rui Huang, Taeg Ki Lim
  • Patent number: 8217501
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Grant
    Filed: May 28, 2010
    Date of Patent: July 10, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 8067831
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 8067275
    Abstract: An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.
    Type: Grant
    Filed: December 17, 2007
    Date of Patent: November 29, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: WonJun Ko, Jong Wook Ju, SeungYong Chai, Taeg Ki Lim, Ja Eun Yun
  • Patent number: 7969023
    Abstract: An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation.
    Type: Grant
    Filed: June 19, 2008
    Date of Patent: June 28, 2011
    Assignee: Stats Chippac Ltd.
    Inventors: Taeg Ki Lim, JaEun Yun, Byung Joon Han
  • Publication number: 20100279504
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts and an integrated circuit; providing a structure over the substrate with only a honeycomb meshwork of posts contacting the top surface of the substrate; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that expose the electrical contacts.
    Type: Application
    Filed: July 12, 2010
    Publication date: November 4, 2010
    Inventors: Heap Hoe Kuan, Hamid Eslampour, DaeSik Choi, Rui Huang, Taeg Ki Lim
  • Publication number: 20100237488
    Abstract: A method of manufacture of an integrated circuit package system includes: providing a substrate with a top surface; configuring the top surface to include electrical contacts; attaching an integrated circuit to the top surface; and depositing a material to prevent warpage of the substrate on the top surface of the substrate and over the integrated circuit, the material patterned to have discrete hollow conduits that are over and larger than the electrical contacts.
    Type: Application
    Filed: May 28, 2010
    Publication date: September 23, 2010
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Patent number: 7737539
    Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.
    Type: Grant
    Filed: January 12, 2006
    Date of Patent: June 15, 2010
    Assignee: STATS Chippac Ltd.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Publication number: 20100123242
    Abstract: A method of manufacture of a semiconductor package system includes: attaching an internal stacking module die to a surface of an internal stacking module substrate having an internal stacking module bonding pad along an edge of an opposite surface thereof; and attaching a support carrier to support the internal stacking module substrate by two edges thereof with the internal stacking module bonding pad exposed.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 20, 2010
    Inventors: Jong-Woo Ha, Sung Yoon Lee, Taeg Ki Lim
  • Patent number: 7656017
    Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.
    Type: Grant
    Filed: December 10, 2007
    Date of Patent: February 2, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Hyun Joung Kim, Taeg Ki Lim, Ja Eun Yun
  • Publication number: 20090189275
    Abstract: An integrated circuit package system includes: providing a singulated, layered structure equivalent in size to an integrated circuit die and having an adhesive layer, an electrical insulator layer, and a heat slug; attaching the integrated circuit die to a base; attaching bond wires to a top of the base for electrical connection between the integrated circuit die and the base; attaching the singulated, layered structure to the integrated circuit die wherein the bond wires are surrounded by the adhesive layer; and encapsulating the integrated circuit die and a portion of the heat slug with a molding compound.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Inventors: WonJun Ko, Taeg Ki Lim, Sungmin Song
  • Publication number: 20090191029
    Abstract: The present invention provides a system for handling semiconductor dies, comprising providing a semiconductor die adhered to a tacky tape, cooling the semiconductor die and the tacky tape to reduce the adhesion between the semiconductor die and the tacky tape, separating the semiconductor die from the tacky tape, and moving the semiconductor die.
    Type: Application
    Filed: January 30, 2008
    Publication date: July 30, 2009
    Inventors: Taeg Ki Lim, Jason Lee, Gab Yong Min, Jung Ho Kim
  • Publication number: 20090155961
    Abstract: An integrated circuit package system comprising: providing a base substrate; attaching a base integrated circuit die over the base substrate; forming a support over the base substrate near only one edge of the base substrate; and attaching a stack substrate over the support and the base integrated circuit die.
    Type: Application
    Filed: December 17, 2007
    Publication date: June 18, 2009
    Inventors: WonJun Ko, Jong Wook Ju, SeungYong Chai, Taeg Ki Lim, Ja Eun Yun
  • Publication number: 20090020893
    Abstract: An integrated circuit package in package system includes: providing a substrate with a first wire-bonded die mounted thereover, and connected to the substrate with bond wires; mounting a triple film spacer above the first wire-bonded die, the triple film spacer having fillers in a first film and in a third film, and having a second film separating the first film and the third film, and the bond wires connecting the first wire-bonded die to the substrate are embedded in the first film; and encapsulating the first wire-bonded die, the bond wires, and the triple film spacer with an encapsulation.
    Type: Application
    Filed: June 19, 2008
    Publication date: January 22, 2009
    Inventors: Taeg Ki Lim, JaEun Yun, Byung Joon Han
  • Patent number: 7443037
    Abstract: A stacked integrated circuit package system is provided connecting an interconnect between a first integrated circuit device and a substrate, the first integrated circuit device on the substrate, applying a protective dot on the first integrated circuit device, mounting a second integrated circuit device, having an adhesive, on the protective dot, with the adhesive on the first integrated circuit device, connecting the second integrated circuit device and the substrate, and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.
    Type: Grant
    Filed: April 1, 2006
    Date of Patent: October 28, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Hyun Joung Kim, Jong Wook Ju, Taeg Ki Lim
  • Publication number: 20080142943
    Abstract: An integrated circuit package system includes providing a plurality of substrates; inserting a receptor in one of the substrates, the receptor held in and not extending through the one of the substrates; inserting a conductive post in another of the substrates; mounting the one of the substrates and the another of the substrates over one another with the conductive post engaging the receptor to thermally interlock without a separate bonding material; and mounting an integrated circuit mounted on the one of the substrates or the another of the substrates.
    Type: Application
    Filed: December 10, 2007
    Publication date: June 19, 2008
    Inventors: Hyun Joung Kim, Taeg Ki Lim, Ja Eun Yun
  • Publication number: 20070296086
    Abstract: An integrated circuit package system is provided including mounting a first integrated circuit device over a carrier, mounting a second integrated circuit device having an adhesive spacer over the first integrated circuit device in an offset configuration, connecting a first internal interconnect between the carrier and the first integrated circuit device with the first internal interconnect within the adhesive spacer, connecting a second internal interconnect between the carrier and the second integrated circuit device, and encapsulating the first integrated circuit device, the second integrated circuit device, the first internal interconnect and the second internal interconnect.
    Type: Application
    Filed: June 12, 2007
    Publication date: December 27, 2007
    Inventors: Jong Wook Ju, Taeg Ki Lim, Hyun Joung Kim