Patents by Inventor Taeg Ki Lim

Taeg Ki Lim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070229107
    Abstract: A stacked integrated circuit package system is provided connecting an interconnect between a first integrated circuit device and a substrate, the first integrated circuit device on the substrate, applying a protective dot on the first integrated circuit device, mounting a second integrated circuit device, having an adhesive, on the protective dot, with the adhesive on the first integrated circuit device, connecting the second integrated circuit device and the substrate, and encapsulating the first integrated circuit device, the second integrated circuit device, and the interconnect.
    Type: Application
    Filed: April 1, 2006
    Publication date: October 4, 2007
    Applicant: STATS ChipPAC Ltd.
    Inventors: Hyun Joung Kim, Jong Wook Ju, Taeg Ki Lim
  • Publication number: 20070158806
    Abstract: An integrated circuit package system including a substrate with a top surface and a bottom surface. Configuring the top surface to include electrical contacts formed between a perimeter of the substrate and a semiconductor die. Aligning over the top surface of the substrate a mold plate with a honeycomb meshwork of posts or a stepped honeycomb meshwork of posts and depositing a material to prevent warpage of the substrate between the top surface of the substrate and the mold plate. Removing the mold plate to reveal discrete hollow conduits formed within the material that align with the electrical contacts.
    Type: Application
    Filed: January 12, 2006
    Publication date: July 12, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyeog Chan Kwon, Hyun Joung Kim, Jae Chang Kim, Taeg Ki Lim, Jong Wook Ju
  • Publication number: 20070063331
    Abstract: An integrated circuit package system is provided including forming a first substrate, mounting a first integrated circuit to the first substrate, and forming first planar interconnects in contact with the first integrated circuit and electrically connecting the first integrated circuit to the first substrate.
    Type: Application
    Filed: September 16, 2005
    Publication date: March 22, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hyeog Chan Kwon, Tae Sung Jeong, Jae Han Chung, Taeg Ki Lim, Jong Wook Ju