Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

Abstract: A flip-flop circuit includes a first unit configured to receive a reference clock signal and a reset signal, and a second unit configured to change an output node to a first level in response to the reference clock signal and change the output node to a second level by precharging the output node in response to a signal output from the first unit according to the reset signal.

Abstract: An equalizer circuit includes an input terminal, a pull-up driving unit suitable for pull-up driving an output terminal based on a signal of the input terminal, a pull-down driving unit suitable for pull-down driving the output terminal, and a capacitor connected between the input terminal and the output terminal.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A duty ratio correction circuit includes a duty cycle ratio controlling unit configured to generate an internal clock signal having a duty cycle ratio defined according to a first reference clock signal and a reset signal and a reset signal generating unit configured to generate the reset signal in response to a second reference clock signal and the internal clock signal fed back thereto.

Abstract: A resistive memory apparatus includes a sensing voltage generation unit and a memory cell. The sensing voltage generation unit configured to drive a sensing node to a voltage with a predetermined level in response to a reference voltage and a voltage of the sensing node. The memory cell is connected with the sensing node and configured to change a magnitude of current flowing through the sensing node according to a resistance value thereof.

Abstract: A semiconductor memory apparatus includes a resistive memory cell; a data sensing unit configured to sense an output voltage, formed by a sensing current supplied to the resistive memory cell, based on a reference voltage, and output data having a value corresponding to the sensing result; and a reference voltage generation unit comprising a dummy memory cell including first and second resistors having first and second resistance values, respectively, and configured to output a voltage formed by the sensing current supplied to the dummy memory cell as the reference voltage.

Abstract: A semiconductor device includes a plurality of driving units configured to drive an output node based on an input signal and be on/off controlled based on driving force control codes, respectively, a slew rate control signal generation block configured to generate a slew rate control signal based on the driving force control codes, and a plurality of signal delay units configured to delay the input signal by respectively different delay amounts, transfer resultant signals to the plurality of driving units, and be respectively controlled in their delay amounts based on the slew rate control signal.

Abstract: A resistive memory device includes a plurality of memory cells, each of which is configured to store a normal data, a first reference data corresponding to a first resistance state and a second reference data corresponding to a second resistance state, a data copy unit configured to temporarily store the normal data read from a selected memory cell and generate a copied cell current based on the stored normal data, a mirroring block configured to temporarily store the first and second reference data read from the selected memory cell, and to generate a first reference current and a second reference current based on the stored first and second reference data, respectively, and a sensing unit configured to sense the stored normal data based on the copied cell current and the first reference current and the second reference current.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A semiconductor memory device has a duty cycle correction circuit capable of outputting a duty cycle corrected clock and its inverted clock having substantially exactly 180° phase difference therebetween. The semiconductor memory device includes a duty cycle corrector configured to receive a first clock and a second clock to generate a first output clock and a second output clock whose duty cycle ratios are corrected in response to correction signals, and a clock edge detector configured to generate the correction signals corresponding to an interval between a reference transition timing of the first output clock and a reference transition timing of the second output clock.

Abstract: A semiconductor apparatus includes an odd data clock buffer group configured to maintain or shift a phase of a multi-phase source clock signal, and output a first multi-phase clock signal, an even data clock buffer group configured to maintain or shift a phase of the multi-phase source clock signal, and output a second multi-phase clock signal, an odd data output buffer group configured to drive odd data in response to the first multi-phase clock signal and output the driven data to an odd data pad group, and an even data output buffer group configured to drive even data in response to the second multi-phase clock signal and output the driven data to an even data pad group, wherein the phases of clock signals of the first and second multi-phase clock signal are different from each other.

Abstract: A filtering circuit includes a clock selection unit configured to transfer a first clock or a second clock having a frequency lower than the first clock as an operating clock in response to a frequence signal, and a filter configured to filter an input signal and generate a filtered signal in synchronization with the operating clock.

Abstract: A non-volatile memory device includes a memory cell including a resistance variable device and a switching unit for controlling a current flowing through the resistance variable device; a read reference voltage generator configured to generate a reference voltage according to a skew occurring in the switching unit; and a sense amplifier configured to sense a voltage corresponding to the current that flows through the resistance variable device based on the reference voltage.

Abstract: A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

Abstract: A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.