Patents by Inventor Tai-Chun Huang

Tai-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098584
    Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.
    Type: Application
    Filed: March 2, 2020
    Publication date: April 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Po-Hsien Cheng, Jr-Hung Li, Tai-Chun Huang, Tze-Liang Lee, Chung-Ting Ko, Jr-Yu Chen, Wan-Chen Hsieh
  • Patent number: 10937686
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: March 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
  • Publication number: 20210028108
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: October 8, 2020
    Publication date: January 28, 2021
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Patent number: 10879377
    Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: December 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Cyuan Lu, Tai-Chun Huang
  • Patent number: 10867807
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Publication number: 20200387191
    Abstract: The disclosure provides an adjustable fixing assembly. The adjustable fixing assembly includes a base plate and a cover plate. The cover plate includes a plate portion and a protrusion portion protruding from the plate portion. The cover plate includes a first installation position and a second installation position. When the cover plate is in the first installation position, the protrusion portion extends away from the base plate, and the cover plate is spaced apart from the base plate by a first minimum distance. When the cover plate is in the second installation position, the protrusion portion extends towards the base plate, and the cover plate is spaced apart from the base plate by a second minimum distance, where the second minimum distance is smaller than the first minimum distance.
    Type: Application
    Filed: December 13, 2019
    Publication date: December 10, 2020
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Shiang-Chun TSAU, Chen-Wei HUANG, Chun-Ying YANG, Ying-Chao PENG, Hsiang-Yun LU, Tai-Yi CHIANG
  • Publication number: 20200373154
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 26, 2020
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Publication number: 20200343384
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Application
    Filed: July 13, 2020
    Publication date: October 29, 2020
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200295131
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Yen-Chun HUANG, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20200252211
    Abstract: A method for generating a random number is used for a plurality of blocks in a blockchain. The method comprises the steps of: selecting a committee comprising a subset of nodes from the blockchain; executing a distributed key generation to generate a share key and a public key at each of the nodes, wherein the public key further comprises a set of verification keys; broadcasting a share signature from each of the nodes; executing a threshold signature at each of the nodes when a new block is generated; and executing a random number which is a hash value of the threshold signature which is combined from a plurality of partial signature generated from the nodes.
    Type: Application
    Filed: January 31, 2020
    Publication date: August 6, 2020
    Inventors: TAI-YUAN CHEN, WEI-NING HUANG, PO-CHUN KUO, HAO CHUNG
  • Patent number: 10734227
    Abstract: A four-layer photoresist and method of forming the same are disclosed. In an embodiment, a method includes forming a semiconductor fin; depositing a target layer on the semiconductor fin; depositing a BARC layer on the target layer; depositing a first mask layer over the BARC layer, the first mask layer being deposited using a plasma process with an RF power of less than 50 W; depositing a second mask layer over the first mask layer using a plasma process with an RF power of less than 500 W; depositing a photoresist layer over the second mask layer; patterning the photoresist layer, the second mask layer, the first mask layer, and the BARC layer to form a first mask; and selectively removing the target layer from a first portion of the semiconductor fin using the first mask, the target layer remaining on a second portion of the semiconductor fin.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: August 4, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Dong-Sheng Li, Chia-Hui Lin, Kai Hung Cheng, Yao-Hsu Sun, Wen-Cheng Wu, Bo-Cyuan Lu, Sung-En Lin, Tai-Chun Huang
  • Publication number: 20200235214
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming a gate structure over a fin structure, forming a source/drain structure in the fin structure and adjacent to the gate structure, forming a dielectric layer over the gate structure and the source/drain structure, and forming an opening in the dielectric layer to expose the source/drain structure. The method further includes depositing a barrier layer lining a sidewall surface of the opening and a top surface of the source/drain structure. The method further includes etching a portion of the barrier layer to expose the source/drain structure. The method further includes depositing a glue layer covering the sidewall surface of the opening and the source/drain structure in the opening. The method further includes forming a contact structure filling the opening in the dielectric layer. The contact structure is surrounded by the glue layer.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Patent number: 10714620
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Publication number: 20200204351
    Abstract: A method for building agreements among a plurality of nodes in a distributed system to improve the throughput of the distributed system is disclosed. The method comprises performing a first Byzantine Agreement protocol; selecting a first leader node from the plurality of nodes; broadcasting a fast message from the first leader node to all other nodes when a clock is equal to 0; determining whether the first leader node decides a block according to a number of a plurality of fast-vote messages received from all other nodes by the first leader node and a value of the clock; and performing a second Byzantine Agreement protocol if it is determined that the first leader node cannot decide a block.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 25, 2020
    Inventors: Tai-Yuan CHEN, Wei-Ning HUANG, Po-Chun KUO, Hao CHUNG
  • Patent number: 10672866
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20200153615
    Abstract: A method for a node to issue a new block is used for a distributed system in which transactions and records are organized in block. The method comprises the steps of: determining a value R from a common reference string; computing a value s associated to a value of a status with a private key at a node, wherein the private key is a private signing key corresponding to the node, and the value s can only be computed by the node with the private key; computing a value r by taking the value s into a function H at the node, wherein the value r is unpredictable and unique to other nodes; and determining whether the node obtains a right to issue a new block by taking the values R and r into a function V.
    Type: Application
    Filed: November 8, 2019
    Publication date: May 14, 2020
    Inventors: Tai-Yuan CHEN, Wei-Ning HUANG, Po-Chun KUO, Hao CHUNG, Tzu-Wei CHAO
  • Patent number: 10643902
    Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: May 5, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chun Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang
  • Patent number: 10629693
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen Huang, Chung-Ting Ko, Hong-Hsien Ke, Chia-Hui Lin, Tai-Chun Huang
  • Publication number: 20200083109
    Abstract: A cut-last process for cutting fin segments of a FinFET structure on a substrate utilizes a two-step process. After the fins are formed, an oxide material is deposited in the trenches of the FinFET structure. The oxide material can be an STI oxide or a low-stress dummy gapfill material. A fin segment can be removed by an etchant and can leave a concave shaped (such as a u-shape or v-shape) portion of silicon at the bottom of the fin. Where the oxide material is an STI oxide, the void left by removing the fin can be filled with replacement STI oxide. Where the oxide material is a dummy gapfill material, the dummy gapfill material can be removed and replaced with an STI oxide or converted to an STI oxide and filled with replacement STI oxide before or after the conversion.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 12, 2020
    Inventors: Yen-Chun Huang, Chih-Tang Peng, Kuang-Yuan Hsu, Tai-Chun Huang, Tsu-Hsiu Perng, Tien-I Bao