Patents by Inventor Tai-Chun Huang

Tai-Chun Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190181247
    Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.
    Type: Application
    Filed: February 18, 2019
    Publication date: June 13, 2019
    Inventors: Bo-Cyuan Lu, Tai-Chun Huang
  • Patent number: 10316411
    Abstract: An injector for forming films respectively on a stack of wafers is provided. The injector includes a plurality of hole structures. Every adjacent two of the wafers have therebetween a wafer spacing, and each of the wafers has a working surface. The hole structures respectively correspond to the respective wafer spacings. The working surface and a respective hole structure have therebetween a parallel distance. The parallel distance is larger than a half of the wafer spacing. A wafer processing apparatus and a method for forming films respectively on a stack of wafers are also provided.
    Type: Grant
    Filed: March 23, 2015
    Date of Patent: June 11, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Che Hsieh, Brian Wang, Tze-Liang Lee, Yi-Hung Lin, Hao-Ming Lien, Shiang-Rung Tsai, Tai-Chun Huang
  • Publication number: 20190157405
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a gate spacer, a source/drain structure, a contact structure, a glue layer and a barrier layer. The gate structure is positioned over a fin structure. The gate spacer is positioned over the fin structure and on a sidewall surface of the gate structure. The source/drain structure is positioned in the fin structure and adjacent to the gate spacer. The contact structure is positioned over the source/drain structure. The glue layer covers a bottom surface and a sidewall surface of the contact structure. The barrier layer encircles the sidewall surface of the contact structure. A bottom surface of the glue layer is exposed to the barrier layer.
    Type: Application
    Filed: May 30, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Chung-Ting KO, Hong-Hsien KE, Chia-Hui LIN, Tai-Chun HUANG
  • Publication number: 20190140076
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: December 17, 2018
    Publication date: May 9, 2019
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20190123204
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Application
    Filed: December 21, 2018
    Publication date: April 25, 2019
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 10269937
    Abstract: An integrated circuit device includes a semiconductor substrate, and a semiconductor strip extending into the semiconductor substrate. A first and a second dielectric region are on opposite sides of, and in contact with, the semiconductor strip. Each of the first dielectric region and the second dielectric region includes a first portion level with the semiconductor strip, and a second portion lower than the semiconductor strip. The second portion further includes a portion overlapped by the semiconductor strip.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: April 23, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tai-Chun Huang, Chih-Tang Peng, Chia-Wei Chang, Ming-Hua Yu, Hao-Ming Lien, Chao-Cheng Chen, Tze-Liang Lee
  • Publication number: 20190088499
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: March 21, 2019
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10211318
    Abstract: A method of manufacturing a semiconductor device comprises forming a spacer material on the semiconductor fin and the gate stack, wherein the forming the spacer material further comprises using atomic layer deposition to deposit a first material on the semiconductor fin and using atomic layer deposition to deposit a second material on the first material, wherein the second material is different from the first material. The spacer material is removed from the semiconductor fin, wherein the removing the spacer material further comprises implanting an etching modifier into the spacer material to form a modified spacer material and removing the modified spacer material.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: February 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bo-Cyuan Lu, Tai-Chun Huang
  • Publication number: 20190006228
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor device having an enhanced gap fill layer in trenches. The present disclosure provides a novel gap fill layer formed using a multi-step deposition and in-situ treatment process. The deposition process can be a flowable chemical vapor deposition (FCVD) utilizing one or more assist gases and molecules of low reactive sticking coefficient (RSC). The treatment process can be an in-situ process after the deposition process and includes exposing the deposited gap fill layer to plasma activated assist gas. The assist gas can be formed of ammonia. The low RSC molecule can be formed of trisilylamin (TSA) or perhydropolysilazane (PHPS).
    Type: Application
    Filed: January 22, 2018
    Publication date: January 3, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jian-Shiou Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang, Yen-Chun Huang
  • Patent number: 10170318
    Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.
    Type: Grant
    Filed: February 6, 2018
    Date of Patent: January 1, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bang-Tai Tang, Tai-Chun Huang
  • Patent number: 10164114
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao
  • Patent number: 10157997
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180350906
    Abstract: A method includes depositing a first dielectric layer in an opening, the first dielectric layer comprising a semiconductor element and a non-semiconductor element. The method further includes depositing a semiconductor layer on the first dielectric layer, the semiconductor layer comprising a first element that is the same as the semiconductor element. The method further includes introducing a second element to the semiconductor layer wherein the second element is the same as the non-semiconductor element. The method further includes applying a thermal annealing process to the semiconductor layer to change the semiconductor layer into a second dielectric layer.
    Type: Application
    Filed: July 24, 2018
    Publication date: December 6, 2018
    Inventors: Yen-Chun Huang, Bor Chiuan Hsieh, Pei-Ren Jeng, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180350693
    Abstract: A method includes performing an atomic layer deposition (ALD) process to deposit a dielectric material over a substrate, curing the deposited dielectric material using an ultra violet (UV) light, and annealing the deposited dielectric material after the curing.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Inventors: Yen-Chun Huang, Bang-Tai Tang, Chih-Tang Peng, Tai-Chun Huang
  • Patent number: 10134604
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: November 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Publication number: 20180315830
    Abstract: A method includes forming a dummy gate stack on a substrate, forming a spacer layer on the dummy gate stack, forming an etch stop layer over the spacer layer and the dummy gate stack, the etch stop layer comprising a vertical portion and a horizontal portion, and performing a densification process on the etch stop layer, wherein the horizontal portion is denser than the vertical portion after the densification process The method also includes forming an oxide layer over the etch stop layer, performing an anneal process on the oxide layer and the etch stop layer, wherein the vertical portion has a greater concentration of oxygen than the horizontal portion after the anneal process.
    Type: Application
    Filed: August 2, 2017
    Publication date: November 1, 2018
    Inventors: Bor Chiuan Hsieh, Chung-Ting Ko, Ting-Gang Chen, Chien Chung Huang, Tai-Chun Huang, Tze-Liang Lee
  • Publication number: 20180315608
    Abstract: A semiconductor device and a method of forming the semiconductor device are disclosed. A method includes forming a gate stack over a semiconductor structure. The gate stack is recessed to form a first recess. A first dielectric layer is formed along a bottom and sidewalls of the first recess, the first dielectric layer having a first etch rate. A second dielectric layer is formed over the first dielectric layer, the second dielectric layer having a second etch rate, the first etch rate being higher than the second etch rate. A third dielectric layer is formed over the second dielectric layer. An etch rate of a portion of the third dielectric layer is altered. The first dielectric layer, the second dielectric layer, and the third dielectric layer are recessed to form a second recess. A capping layer is formed in the second recess.
    Type: Application
    Filed: February 6, 2018
    Publication date: November 1, 2018
    Inventors: Bang-Tai Tang, Tai-Chun Huang
  • Publication number: 20180315618
    Abstract: A method includes forming a metal gate structure over a first fin, where the metal gate structure is surrounded by a first dielectric material, and forming a capping layer over the first dielectric material, where an etch selectivity between the metal gate structure and the capping layer is over a pre-determined threshold. The method also includes forming a patterned hard mask layer over the first fin and the first dielectric material, where an opening of the patterned hard mask layer exposes a portion of the metal gate structure and a portion of the capping layer. The method further includes removing the portion of the metal gate structure exposed by the opening of the patterned hard mask layer.
    Type: Application
    Filed: October 5, 2017
    Publication date: November 1, 2018
    Inventors: Ming-Jie Huang, Syun-Ming Jang, Ryan Chia-Jen Chen, Ming-Ching Chang, Shu-Yuan Ku, Tai-Chun Huang, Chunyao Wang, Tze-Liang Lee, Chi On Chui
  • Patent number: 10103141
    Abstract: A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.
    Type: Grant
    Filed: February 12, 2016
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien
  • Publication number: 20180277681
    Abstract: An embodiment is a method including recessing a gate electrode over a semiconductor fin on a substrate to form a first recess from a top surface of a dielectric layer, forming a first mask in the first recess over the recessed gate electrode, recessing a first conductive contact over a source/drain region of the semiconductor fin to form a second recess from the top surface of the dielectric layer, and forming a second mask in the second recess over the recessed first conductive contact.
    Type: Application
    Filed: May 29, 2018
    Publication date: September 27, 2018
    Inventors: Chin-Hsiang Lin, Tai-Chun Huang, Tien-I Bao