Patents by Inventor Tai-Ju Chen

Tai-Ju Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220285522
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Application
    Filed: May 26, 2022
    Publication date: September 8, 2022
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Patent number: 11380777
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: July 5, 2022
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Publication number: 20220165864
    Abstract: A semiconductor substrate is provided. A trench isolation region is formed in the semiconductor substrate. A resist pattern having an opening exposing the trench isolation region and partially exposing the semiconductor substrate is disposed adjacent to the trench isolation region. A first ion implantation process is performed to implant first dopants into the semiconductor substrate through the opening, thereby forming a well region in the semiconductor substrate. The trench isolation region is within the well region. A second ion implantation process is performed to implant second dopants into the semiconductor substrate through the opening, thereby forming an extended doped region contiguous with the well region. The resist pattern is then removed. After removing the resist pattern, a gate dielectric layer is formed on the semiconductor substrate. A gate is then formed on the gate dielectric layer. The gate overlaps with the extended doped region.
    Type: Application
    Filed: November 23, 2020
    Publication date: May 26, 2022
    Inventors: Zhi-Cheng Lee, Wei-Jen Chen, Kai-Lin Lee, Tai-Ju Chen
  • Patent number: 10103248
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: October 16, 2018
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Patent number: 9741830
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: August 22, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20170207322
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The method includes: providing a substrate with a fin structure to define a first and a second type well regions; forming a trench in the first-type well region to separate the fin structure into a first part and a second part; forming a STI structure in the trench; forming a first and a second polycrystalline silicon gate stack structures at the fin structure; forming discontinuous openings on the exposed fin structure and growing an epitaxial material layer in the openings; doping the epitaxial material layer to form a drain and a source doped layers in the first and second parts respectively; and performing a RMG process to replace the first and second polycrystalline silicon gate stack structures with a first and second metal gate stack structures respectively.
    Type: Application
    Filed: March 8, 2017
    Publication date: July 20, 2017
    Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
  • Patent number: 9640663
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Grant
    Filed: December 29, 2014
    Date of Patent: May 2, 2017
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Tai-Ju Chen, Yi-Han Ye, Te-Chih Chen
  • Publication number: 20160225880
    Abstract: The present invention provides a method of forming a metal oxide semiconductor (MOS) device comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and a part thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: April 7, 2016
    Publication date: August 4, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160155837
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 2, 2016
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Publication number: 20160141420
    Abstract: A high-voltage FinFET device having LDMOS structure and a method for manufacturing the same are provided. The high-voltage FinFET device includes: at least one fin structure, a working gate, a shallow trench isolation structure, and a first dummy gate. The fin structure includes a first-type well region and a second-type well region adjacent to the first-type well region, and further includes a first part and a second part. A trench is disposed between the first part and the second part and disposed in the first-type well region. A drain doped layer is disposed on the first part which is disposed in the first-type well region, and a source doped layer is disposed on the second part which is disposed in the second-type well region. The working gate is disposed on the fin structure which is disposed in the first-type well region and in the second-type well region.
    Type: Application
    Filed: December 29, 2014
    Publication date: May 19, 2016
    Inventors: TAI-JU CHEN, YI-HAN YE, TE-CHIH CHEN
  • Patent number: 9337339
    Abstract: The present invention provides a metal oxide semiconductor (MOS) device, comprising a gate structure and an epitaxial structure. The gate structure is disposed on a substrate. The epitaxial structure is disposed in the substrate at two sides of the gate structure and apart thereof serves a source/drain of the MOS, wherein the epitaxial structure comprises: a first buffer layer with a second conductive type, a second buffer layer, and an epitaxial layer with a first conductive type complementary to the second conductive type. The present invention further provides a method of forming the same.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 10, 2016
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kung-Hong Lee, Chun-Jung Tang, Te-Chih Chen, Tai-Ju Chen
  • Patent number: 8043919
    Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: October 25, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Ju Chen, Tung-Hsing Lee, Da-Kung Lo
  • Publication number: 20090124056
    Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.
    Type: Application
    Filed: November 12, 2007
    Publication date: May 14, 2009
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Tai-Ju Chen, Tung-Hsing Lee, Da-Kung Lo
  • Publication number: 20030008515
    Abstract: A gate mask is formed on a silicon substrate of a semiconductor wafer followed by etching region of the silicon substrate not covered by the gate mask to a predetermined depth. Subsequently, a silicon oxide layer is formed on the region of the silicon substrate not covered by the gate mask. A first conductive layer and a second conductive layer are formed respectively on the silicon substrate. Then, a first etching back process is performed to form a spacer consisting of the second conductive layer, the first conductive layer and the silicon oxide layer on the region of the silicon substrate below the gate mask. After the gate mask is removed, a selective etching process is performed to remove portions of both the first conductive layer and the silicon oxide layer to form the spacer into an undercut profile. Finally, a doping process and an ion implantation process are performed, respectively, to form lightly doped drains (LDDs) and a source/drain (S/D) of a vertical MOS transistor.
    Type: Application
    Filed: July 3, 2001
    Publication date: January 9, 2003
    Inventors: Tai-Ju Chen, Hua-Chou Tseng
  • Patent number: 6489206
    Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.
    Type: Grant
    Filed: March 22, 2001
    Date of Patent: December 3, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Ju Chen, Hua-Chou Tseng
  • Publication number: 20020155700
    Abstract: A method of forming a damascene structure. A porous dielectric layer is formed over a substrate. The porous dielectric layer is patterned to form an opening that exposes a portion of the substrate. A conformal low dielectric constant layer is formed over the substrate and the exposed surface of the opening. A portion of the low dielectric constant material is removed to form spacers on the sidewalls of the porous dielectric layer. A conformal barrier layer and a conductive layer are sequentially formed over the opening. Excess conductive material and barrier material outside the opening above the dielectric layer are removed to form a damascene structure.
    Type: Application
    Filed: May 31, 2001
    Publication date: October 24, 2002
    Inventors: Tai-Ju Chen, Chien-Hsing Lin
  • Publication number: 20020137306
    Abstract: A method for forming polysilicon-filled trench isolations is provided. The present method is characterized in that using nitrogen implantation to amorphize the top portion of the polysilicon filled in the trench isolation and then a nitrogen-implanted region formed in this top portion. The nitrogen-implanted region forms an oxynitride cap layer during the polysilicon oxidation. The oxynitride cap layer provides better erosive resistance to acidic solutions for stripping away photopresist layers used for several wells/Vth implantations than a silicon dioxide layer. The oxynitride cap layer also reduces the gate-to-channel fringing field because its dielectric constant is higher than that of silicon dioxide. Moreover, the nitrogen-implanted region in the top portion of the polysilicon decreases the polysilicon oxidation time so that the channel edge oxidation is reduced.
    Type: Application
    Filed: March 20, 2001
    Publication date: September 26, 2002
    Inventor: Tai-Ju Chen
  • Publication number: 20020137293
    Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.
    Type: Application
    Filed: February 1, 2002
    Publication date: September 26, 2002
    Applicant: United Microelectronics Corp.
    Inventors: Tai-Ju Chen, Hua-Chou Tseng
  • Publication number: 20020135015
    Abstract: A method for forming a self-aligned local-halo metal-oxide-semiconductor device is provided. The present method is characterized in that a pair of first sidewall spacers is firstly formed on opposite sides of a gate electrode over a semiconductor substrate, and then a pair of second sidewall spacers is formed, each of which formed on one side of each first sidewall spacer. Next, a raised source/drain is formed upward on the substrate between each shallow trench isolation and each second sidewall spacer. Thereafter, the pair of second sidewall spacers is stripped away. Then, the gate electrode and raised source/drain act as the self-aligned ion implant masks, a LDD/Halo implantation is performed to form a local LDD/Halo diffusion region between each shallow trench isolation and each of the first sidewall spacers.
    Type: Application
    Filed: March 22, 2001
    Publication date: September 26, 2002
    Inventors: Tai-Ju Chen, Hua-Chou Tseng
  • Publication number: 20020106864
    Abstract: This invention relates to a method for filling of a shallow trench isolation, more particularly, to a method of gap filling shallow trench isolation with ozone-TEOS. A pad oxide layer is provided over the surface of a substrate. The first nitride layer is deposited overlying the pad oxide layer. A isolation trench is etched through the first nitride and pad oxide layers into the semiconductor substrate. A thermal oxide layer is grown within the isolation trenches. The second silicon nitride layer is deposited over the first nitride layer and over the thermal oxide layer within the isolation trenches. The second silicon nitride layer and the thermal oxide layer which are on the first surface of the isolation trenches are removed by using the anisotropic etching method and the semiconductor substrate is shown. Thereafter, an ozone-TEOS layer is deposited overlying the second silicon nitride layer and the semiconductor substrate and filling the isolation trenche.
    Type: Application
    Filed: February 8, 2001
    Publication date: August 8, 2002
    Inventors: Tai-Ju Chen, Hua-Chou Tseng