Patents by Inventor Taiji Noda
Taiji Noda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230422535Abstract: An imaging device includes a pixel region and a first peripheral region. The pixel region includes a pixel substrate portion and an amplifying transistor that outputs a signal voltage corresponding to an amount of signal charge. The amplifying transistor is located in the pixel substrate portion. The first peripheral region includes a first peripheral substrate portion and a first peripheral transistor. The first peripheral transistor is located in the first peripheral substrate portion. The pixel substrate portion and the first peripheral substrate portion are stacked on each other. At least one type of impurity that contributes to inhibition of transient enhanced diffusion of a conductive impurity is defined as a specific species. The first peripheral transistor includes a first specific layer that is located in the first peripheral substrate portion and that contains the conductive impurity and the specific species.Type: ApplicationFiled: September 8, 2023Publication date: December 28, 2023Inventor: TAIJI NODA
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Publication number: 20220344394Abstract: An imaging device includes a pixel region including an amplifying transistor that includes a first gate and that outputs a signal voltage corresponding to an amount of signal charge, a first peripheral region including at least one first peripheral transistor including a second gate, the first peripheral region being located outside the pixel region, and a semiconductor substrate provided with the amplifying transistor and the at least one first peripheral transistor. A gate length of the second gate is shorter than a gate length of the first gate. When at least one type of impurity that contributes to suppression of transient enhanced diffusion of a conductive impurity is defined as a first specific species, the at least one first peripheral transistor includes a first specific layer located in the semiconductor substrate, the first specific layer containing a conductive impurity and the first specific species.Type: ApplicationFiled: July 8, 2022Publication date: October 27, 2022Inventor: TAIJI NODA
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Publication number: 20220014700Abstract: An imaging device includes a semiconductor substrate and pixels, which includes a first pixel and second pixels adjacent thereto. Each of the pixels includes a first photoelectric conversion layer, a first pixel electrode, a first plug that electrically connects the semiconductor substrate and the first pixel electrode, a second photoelectric conversion layer, a second pixel electrode, and a second plug that electrically connects the semiconductor substrate and the second pixel electrode. In the first pixel and the plurality of second pixels, a distance between the closest plugs of the first plugs and the second plugs is larger than or equal to one-half of a pixel pitch, when viewed in a normal direction of the semiconductor substrate.Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Inventors: TAKAYOSHI YAMADA, YOSHIHIRO SATO, TAIJI NODA
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Patent number: 10446549Abstract: An imaging device includes: a semiconductor substrate including a first impurity region and a second impurity region; a first insulating layer on a portion of a surface of the semiconductor substrate; a second insulating layer on another portion of the surface of the semiconductor substrate, a thickness of the first insulating layer being greater than a thickness of the second insulating layer; a first transistor including: a first gate electrode facing the surface of the semiconductor substrate via the first insulating layer; the first impurity region as one of a source and a drain; and the second impurity region as the other of the source and the drain; and a photoelectric converter electrically connected to the first impurity region. The first insulating layer covers the first impurity region, and the second insulating layer covers the second impurity region.Type: GrantFiled: April 15, 2019Date of Patent: October 15, 2019Assignee: Panasonic Intellectual Property Management Co., Ltd.Inventors: Yoshihiro Sato, Ryota Sakaida, Satoshi Shibata, Taiji Noda
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Publication number: 20190244959Abstract: An imaging device includes: a semiconductor substrate including a first impurity region and a second impurity region; a first insulating layer on a portion of a surface of the semiconductor substrate; a second insulating layer on another portion of the surface of the semiconductor substrate, a thickness of the first insulating layer being greater than a thickness of the second insulating layer; a first transistor including: a first gate electrode facing the surface of the semiconductor substrate via the first insulating layer; the first impurity region as one of a source and a drain; and the second impurity region as the other of the source and the drain; and a photoelectric converter electrically connected to the first impurity region. The first insulating layer covers the first impurity region, and the second insulating layer covers the second impurity region.Type: ApplicationFiled: April 15, 2019Publication date: August 8, 2019Inventors: Yoshihiro SATO, Ryota SAKAIDA, Satoshi SHIBATA, Taiji NODA
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Patent number: 10304828Abstract: An imaging device includes: a semiconductor substrate; a first insulating layer covering a surface of the semiconductor substrate, the first insulating layer including first and second portions, a thickness of the first portion being greater than a thickness of the second portion; and an imaging cell. The imaging cell includes: a first transistor including a first gate insulating layer and an impurity region in the semiconductor substrate as one of a source and a drain; a second transistor including a gate electrode and a second gate insulating layer; and a photoelectric converter electrically connected to the gate electrode and the impurity region. The first portion covers a portion of the impurity region, the portion being exposed to the surface of the semiconductor substrate. The first gate insulating layer is a part of the first portion. The second gate insulating layer is a part of the second portion.Type: GrantFiled: September 7, 2017Date of Patent: May 28, 2019Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Yoshihiro Sato, Ryota Sakaida, Satoshi Shibata, Taiji Noda
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Publication number: 20180083004Abstract: An imaging device includes: a semiconductor substrate; a first insulating layer covering a surface of the semiconductor substrate, the first insulating layer including first and second portions, a thickness of the first portion being greater than a thickness of the second portion; and an imaging cell. The imaging cell includes: a first transistor including a first gate insulating layer and an impurity region in the semiconductor substrate as one of a source and a drain; a second transistor including a gate electrode and a second gate insulating layer; and a photoelectric converter electrically connected to the gate electrode and the impurity region. The first portion covers a portion of the impurity region, the portion being exposed to the surface of the semiconductor substrate. The first gate insulating layer is a part of the first portion. The second gate insulating layer is a part of the second portion.Type: ApplicationFiled: September 7, 2017Publication date: March 22, 2018Inventors: YOSHIHIRO SATO, RYOTA SAKAIDA, SATOSHI SHIBATA, TAIJI NODA
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Patent number: 8350342Abstract: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.Type: GrantFiled: April 15, 2009Date of Patent: January 8, 2013Assignee: Panasonic CorporationInventor: Taiji Noda
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Patent number: 8110897Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.Type: GrantFiled: March 3, 2010Date of Patent: February 7, 2012Assignee: Panasonic CorporationInventor: Taiji Noda
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Publication number: 20100164017Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.Type: ApplicationFiled: March 3, 2010Publication date: July 1, 2010Applicant: PANASONIC CORPORATIONInventor: Taiji NODA
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Publication number: 20090278209Abstract: A semiconductor device includes a gate electrode provided on a semiconductor region with a gate insulating film being interposed therebetween, extension diffusion layers provided in regions on both sides of the gate electrode of the semiconductor region, a first-conductivity type first impurity being diffused in the extension diffusion layers, and source and drain diffusion layers provided in regions farther outside than the respective extension diffusion layers of the semiconductor region and having junction depths deeper than the respective extension diffusion layers. At least one of the extension diffusion layers on both sides of the gate electrode contains carbon.Type: ApplicationFiled: April 15, 2009Publication date: November 12, 2009Inventor: Taiji NODA
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Patent number: 7429771Abstract: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.Type: GrantFiled: April 26, 2005Date of Patent: September 30, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Taiji Noda
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Publication number: 20070063275Abstract: Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×1016/cm2, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.Type: ApplicationFiled: November 21, 2006Publication date: March 22, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTDInventor: Taiji Noda
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Publication number: 20060275964Abstract: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.Type: ApplicationFiled: August 16, 2006Publication date: December 7, 2006Applicant: Matsushita Electric Industrial Co., Inc.Inventor: Taiji Noda
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Patent number: 7141477Abstract: Into a channel formation region of a semiconductor substrate of p-type silicon, indium ions are implanted at an implantation energy of about 70 keV and a dose of about 5×1013/cm2, thereby forming a p-doped channel layer. Next, germanium ions are implanted into the upper portion of the semiconductor substrate at an implantation energy of about 250 keV and a dose of about 1×1016/cm2, thereby forming an amorphous layer in a region of the semiconductor substrate deeper than the p-doped channel layer.Type: GrantFiled: October 2, 2003Date of Patent: November 28, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Taiji Noda
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Patent number: 7138322Abstract: An n-type channel diffused layer and an n-type well diffused layer are formed in the top portion of a semiconductor substrate, and a gate insulating film and a gate electrode are formed on the semiconductor substrate. Using the gate electrode as a mask, boron and arsenic are implanted to form p-type extension implanted layers and n-type pocket impurity implanted layers. Fluorine is then implanted using the gate electrode as a mask to form fluorine implanted layers. The resultant semiconductor substrate is subjected to rapid thermal annealing, forming p-type high-density extension diffused layers and n-type pocket diffused layers. Sidewalls and p-type high-density source/drain diffused layers are then formed.Type: GrantFiled: February 11, 2004Date of Patent: November 21, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Taiji Noda
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Publication number: 20060202287Abstract: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.Type: ApplicationFiled: May 8, 2006Publication date: September 14, 2006Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Taiji Noda, Hiroyuki Umimoto, Shinji Odanaka
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Patent number: 7091093Abstract: A gate electrode is formed over a semiconductor region with a gate insulating film interposed therebetween. An extended high-concentration dopant diffused layer of a first conductivity type is formed in part of the semiconductor region beside the gate electrode through diffusion of a first dopant. A pocket dopant diffused layer of a second conductivity type is formed under the extended high-concentration dopant diffused layer through diffusion of heavy ions. The pocket dopant diffused layer includes a segregated part that has been formed through segregation of the heavy ions.Type: GrantFiled: September 15, 2000Date of Patent: August 15, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Taiji Noda, Hiroyuki Umimoto, Shinji Odanaka
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Publication number: 20060068556Abstract: The semiconductor device of the present invention includes: a gate insulating film formed on a semiconductor region of a first conductivity type; a gate electrode formed on the gate insulating film; and a channel doped layer of the first conductivity type formed in the semiconductor region beneath the gate electrode. The channel doped layer contains carbon as an impurity.Type: ApplicationFiled: July 19, 2005Publication date: March 30, 2006Inventor: Taiji Noda
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Publication number: 20050247977Abstract: A MIS-type semiconductor device includes a p-type semiconductor substrate, a gate insulating film formed on the semiconductor substrate, a gate electrode formed on the gate insulating film, and n-type diffused source and drain layers formed in regions of the semiconductor substrate located below both sides of the gate electrode. Insides of the n-type diffused source and drain layers are formed with p-type impurity implanted regions having a lower p-type impurity concentration than the impurity concentration of the n-type diffused source and drain layer.Type: ApplicationFiled: April 26, 2005Publication date: November 10, 2005Inventor: Taiji Noda