Abstract: A method and apparatus are provided to prevent or reduce stiction of a MEMS device. The MEMS device may include a protrusion extending from a surface of the MEMS device. During manufacture, the protrusion may be connected across an opening in the MEMS device to a sidewall of the substrate. Before manufacture of the MEMS device is completed, at least a portion of the protrusion connecting the MEMS device to the substrate may be removed. During operation, the protrusion may provide stiction prevention or reduction for the surface from which the first protrusion may extend. A plurality of protrusions may be formed along a plurality of surfaces for the MEMS device to prevent or reduce stiction along the corresponding surfaces. Protrusions may also be formed on devices surrounding or encapsulating the MEMS device to prevent or reduce stiction of the MEMS device to the surrounding or encapsulating devices.

Abstract: A junction gate field-effect transistor (JFET) includes a substrate, a source region formed in the substrate, a drain region formed in the substrate, a channel region formed in the substrate, and at least one gate region formed in the substrate. The channel region connects the source and drain regions. The at least one gate region is configured to cause a depletion region in one of the source and drain regions.

Abstract: A semiconductor circuit includes an array of repeating blocks, each of the blocks having a device, and at least one signal line connecting the devices of the blocks. A model of the semiconductor circuit is generated to include a functional area corresponding to at least one first block of the array, and a loading area corresponding to at least one second block of the array. In the functional area, parasitic parameters of the at least one signal line and the device of the at least one first block are extracted. In the loading area, parasitic parameters of the at least one signal line are extracted, but parasitic parameters of the device of the at least one second block are not extracted.

Abstract: Disclosed herein is a method of forming a stress relieved film stack, the method comprising forming a film stack on a first side of a substrate, the film stack comprising a plurality of film layers and creating a plurality of film stack openings according to a cutting pattern and along at least a portion of a buffer region. The plurality of film stack openings extend from a top surface of the film stack to the substrate. A deflection of the substrate may be determined, and the cutting pattern selected prior to creating the film stack openings based on the deflection of the substrate. The substrate may have a deflection of less than about 2 ?m after the creating the plurality of film stack openings. And at least one of the plurality of film layers may comprise one of titanium nitride, silicon carbide and silicon dioxide.

Abstract: A method includes forming a first pattern having a first opening on a semiconductor substrate. The first opening is then filled. A second pattern of a first and second feature, interposed by the filled opening, is formed on the semiconductor substrate. Spacer elements then are formed on sidewalls of the filled opening, the first feature and the second feature. After forming the spacer elements, the material comprising first and second features is removed to form a second opening and a third opening. The filled opening, the second opening and the third opening are used as a masking element to etch a target layer of the substrate.

Abstract: MEMS structures and methods utilizing a locker film are provided. In an embodiment a locker film is utilized to hold and support a moveable mass region during the release of the moveable mass region from a surrounding substrate. By providing additional support during the release of the moveable mass, the locker film can reduce the amount of undesired movement that can occur during the release of the moveable mass, and preventing undesired etching of the sidewalls of the moveable mass.

Abstract: A metal plating apparatus includes a chemical bath chamber, an anode disposed at a bottom portion of the chemical bath chamber, and a cathode disposed at a top portion of the chemical bath chamber. A solenoid coil is disposed within the chemical bath chamber between the anode and the cathode. The solenoid coil is arranged to apply a magnetic field during a metal plating process in a direction from the anode to the cathode.

Abstract: Disclosed are a wafer carrier that keeps wafers under a constant pressure, at any preset value below or above the atmospheric pressure, to prevent wafer contaminations arising from atmospheric exposure in conventional wafer carriers, and also, a wafer transport system and method utilizing the same wafer carrier. The wafer carrier charged with a preset carrier pressure is transported and docked with an airlock of a wafer processing tool comprising the airlock, a vacuum transfer module, and a process chamber. The airlock adjusts, by a gas pump, inner pressure to equate successively with, first, the carrier pressure before opening the carrier door, and next, the vacuum transfer module pressure before opening the latter's door. The wafers are then transferred into the process chamber. After processing, the wafers are transferred back into the wafer carrier and charged with the preset carrier pressure before undocked and transported to the next wafer processing tool.

Abstract: Defect-describing (or “cut”) layer(s) for describing defects associated with different sides of a 3-dimensional (3D) structure enable fault modeling to determine the effect of position and location of defects on transistor performance. One or more defect-describing layers are used to identify the coordinates and sides of the 3D structures of the defects. The defect-describing layer(s) enables fault-modeling for 3D structures to understand the effects of faults on different locations, especially for defects associated with the fins of the finFET devices. Faults are injected to different locations and sides of fins and are modeled with different test vectors, test parameters and testing devices to identify detectable faults. The fault modeling would help identify the sources of defects and also improve layout design of finFET device structures.

Abstract: A semiconductor device, a package structure, and methods of forming the same are disclosed. An embodiment is a semiconductor device comprising a first optical device over a first substrate, a vertical waveguide on a top surface of the first optical device, and a second substrate over the vertical waveguide. The semiconductor device further comprises a lens capping layer on a top surface of the second substrate, wherein the lens capping layer is aligned with the vertical waveguide, and a second optical device over the lens capping layer.

Abstract: Various packages and methods are disclosed. A package according to an embodiment includes a substrate, a chip attached to a surface of the substrate with electrical connectors, a molding compound on the surface of the substrate and around the chip, an adhesive on a surface of the chip that is distal from the surface of the substrate, and a lid on the adhesive. In an embodiment, a region between the molding compound and the lid at a corner of the lid is free from the adhesive. In another embodiment, the lid has a recess in a surface of the lid facing the surface of the molding compound.

Abstract: A method for being used in a lithography process is provided. The method includes receiving a first mask, a second mask and a substrate with a set of baseline registration marks. A first set of registration marks is formed on the substrate using the first mask and a first exposure tool, and a first set of overlay errors is determined. The first set of registration marks is removed and a second set of registration marks is formed on the substrate using the second mask and a second exposure tool. A second set of overlay errors is determined. A set of tool-induced overlay errors is generated from the first and second sets of overlay errors and used in fabricating a third mask. The third mask can then be used in the lithography process to accommodate the overlay errors caused by different exposure tools, different masks, and different mask writers.

Abstract: A method of forming a fin structure of a semiconductor device includes providing a substrate, creating a mandrel pattern over the substrate, depositing a first spacer layer over the mandrel pattern, and removing portions of the first spacer layer to form first spacer fins. The method also includes performing a first fin cut process to remove a subset of the first spacer fins, depositing a second spacer layer over the un-removed first spacer fins, and removing portions of the second spacer layer to form second spacer fins. The method further includes forming fin structures, and performing a second fin cut process to remove a subset of the fin structures.

Abstract: In a timing delay characterization method, a signal path between an input terminal and an output terminal of a semiconductor circuit is divided into an input stage, a processing stage, and an output stage. An operation of the input stage is simulated at various input parameter values of an input parameter at the input terminal to obtain corresponding extrinsic input timing delays associated with the input stage. An operation of the processing stage is simulated to obtain an intrinsic timing delay associated with the processing stage. An operation of the output stage is simulated at various output parameter values of an output parameter at the output terminal to obtain corresponding extrinsic output timing delays associated with the output stage. A timing delay data store is generated or populated based on the extrinsic input timing delays, the extrinsic output timing delays and the intrinsic timing delay.

Abstract: A passive circuit device incorporating a resistor and a capacitor and a method of forming the circuit device are disclosed. In an exemplary embodiment, the circuit device comprises a substrate and a passive device disposed on the substrate. The passive device includes a bottom plate disposed over the substrate, a top plate disposed over the bottom plate, a spacing dielectric disposed between the bottom plate and the top plate, a first contact and a second contact electrically coupled to the top plate, and a third contact electrically coupled to the bottom plate. The passive device is configured to provide a target capacitance and a first target resistance. The passive device may also include a second top plate disposed over the bottom plate and configured to provide a second target resistance, such that the second target resistance is different from the first target resistance.

Abstract: In a method, a layout of a device having a pattern of features is provided. The method continues to include identifying a first portion of at least one feature of the plurality of features. An image criteria for the first portion may be assigned. A lithography optimization parameter is determined based on the assigned image criteria for the first portion. Finally, the first portion of the at least one feature is imaged onto a semiconductor substrate using the determined lithography optimization parameter.

Abstract: A testing holder for a chip unit, a multi site holding frame for plural chip units and a method for testing a die thereof are provided. The proposed multi site holding frame for testing plural chip units simultaneously includes a first holder frame having a plurality of testing holders. Each of the plurality of testing holders includes a holder body containing a specific one of the plural chip units, and a pressure releasing device formed on the holder body to release an insertion pressure when the specific one of the plural chip units is inserted in the holder body.

Abstract: Embodiments of mechanisms for epitaxially growing one or more doped silicon-containing materials to form source and drain regions of finFET devices are provided in this disclosure. The dopants in the one or more doped silicon-containing materials can be driven into the neighboring lightly-doped-drain (LDD) regions by thermal anneal to dope the regions. The epitaxially growing process uses a cyclical deposition/deposition/etch (CDDE) process. In each cycle of the CDDE process, a first and a second doped materials are formed and a following etch removes most of the second doped material. The first doped material has a higher dopant concentration than the second material and is protected from the etching process by the second doped material. The CDDE process enables forming a highly doped silicon-containing material.

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a non-planar portion, a resistive material layer conformally covering the non-planar portion of the bottom electrode; and, a top electrode on the resistive material layer. The via portion of the bottom electrode is embedded in a first RRAM stop layer. The non-planar portion of the bottom electrode has an apex and is centered above the via portion.

Abstract: A method includes receiving a substrate having an etch stop layer deposited over the substrate and a dummy mandrel layer deposited over the etch stop layer, forming a plurality of hard mask patterns using a hard mask layer deposited over the dummy mandrel layer, wherein the hard mask patterns includes a first dimension adjusted by a predetermined value, depositing a first spacer layer over the hard mask patterns, wherein a thickness of the first spacer layer is adjusted by the predetermined value, forming a plurality of spacer fins in the dummy mandrel layer, wherein the spacer fins include a second dimension, a first space, and a second space, performing a first fin cut process to remove at least one spacer fin, adjusting the second dimension to a target dimension, performing a second fin cut process, and forming a plurality of fin structures in the substrate by etching the spacer fins.