Abstract: A wireless communication device is configured to be able to communicate via both a first access point and a second access point for using the first access point to obtain validation credentials in order to permit use of the second access point to access a network. The wireless communication device comprises a processor; and a non-transitory computer readable medium having stored thereon computer executable instructions. The instructions are operable to: initiate communication with the second access point in order to access a network; obtain an access point identifier from the second access point, the access point identifier for identifying the second access point; transmit the access point identifier to a validation server via the first access point; receive validation credentials from the validation server via the first access point; and use the validation credentials to validate the wireless communication device with the second access point to obtain access to the network.

Abstract: A transmitter architecture having a single signal path or hardware to cover WCDMA/EDGE/GSM applications, and requires no SAW at the transmitter outputs. The transmitter architecture allows for a transmit convergence feature. A passive mixer with unique driver and furthermore using native devices available from the CMOS process for the mixer cores enables low voltage and low power design, low output noise and high linearity. A digital variable gain amplifier has the capability to cover wide output dynamic range operated from low supply voltage and interfaced digitally with the baseband circuit without DAC. A single transformer is used to combine the outputs from the WCDMA/EDGE and GSM drivers and subsequently convert the differential signal paths into a single-ended signal. RF switches are used to divert the output from the transformer to different bands and applications.

Abstract: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

Abstract: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Abstract: A method for transmitting data between a client and a server is provided. The method comprising the following steps. The data is segmented into a plurality of data packets, which are scheduled to be transmitted via different ones of a plurality of access points. Each of the plurality of access points is configured to communicate with the client using a different protocol and communicate with the server using a different network path. Each of the plurality of data packets is transmitted between the client and the server via the scheduled access point. A client device and proxy server configured to implement the method are also provided, as is a computer readable medium having stored thereon instructions for implementing the method.

Abstract: A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.

Abstract: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

Abstract: A digital phase lock loop (PLL) circuit having a digital charge pump circuit for providing digital signals corresponding to a difference in phase between an internal clock corresponding to a voltage controlled oscillator, and a reference clock. These digital signals are processed by a digital processing circuit for providing digital control signals. Some of the digital control signals are converted into an analog control signal to provide fine control of the voltage controlled oscillator, while the remaining digital control signals provide coarse control of the voltage controlled oscillator.

Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

Abstract: A power ramping circuit for use in the transmit path of a radio frequency (RF) circuit. The power ramping circuit includes parallel connected transistors used as logarithmic resistor attenuators for adjusting current to a mixer circuit in the transmit path. The parallel connected transistors can be sized differently, and are sequentially turned off to gradually increase the current provided to the mixer circuit. A ramp control circuit controls the parallel connected transistors in response to either an analog signal or a digital signal.

Abstract: A closed loop power output calibration system for variable power output wireless devices. The wireless device includes a wireless transceiver having a transmit core coupled to a discrete power amplifier. Power detection circuitry formed in the wireless transceiver provides a detected power level of the power amplifier, and a reference power level, both of which are converted to digital signals using existing I and Q signal analog to digital converters in the receiver core. The digital signals are processed to cancel power distortion and temperature effects to provide a resulting power feedback signal. Corrective control signals are generated in response to the power feedback signal relative to a desired power output level. The gain in the transmit core is then adjusted in response to the corrective control signals such that the power amplifier outputs the target output power level.

Abstract: The invention is directed at a hybrid modulation apparatus which combines a polar modulation circuit and a linear modulation circuit. The hybrid apparatus allows a communications device to function as a polar or a linear modulation circuit with less components as the output of the linear modulation circuit is an input of the polar modulation circuit.

Abstract: The invention is directed at a hybrid modulation apparatus which combines a polar modulation circuit and a linear modulation circuit. The hybrid apparatus allows a communications device to function as a polar or a linear modulation circuit with less components as the output of the linear modulation circuit is an input of the polar modulation circuit.

Abstract: An integrated automatic IIP2 calibration architecture for wireless transceivers is disclosed. The architecture enables a wireless transceiver to generate a test radio frequency (RF) signal having a second order tone with minimal additional circuitry. In particular, the test RF signal is generated using a combination of native transceiver circuits and test adaptor circuits. Native transceiver circuits are those circuits implemented on the transceiver chip for executing native transceiver functions during normal operation, which can be used for generating the test (RF) signal. Test adaptor circuits are added to the transceiver chip, more specifically to the native circuits, for enabling the native circuits to generate the test RF signal in a self-test mode of operation. Circuits for implementing a particular IIP2 minimizing scheme can be included on the transceiver chip for automatic IIP2 calibration during the self-test mode of operation.

Abstract: There is a need for an inexpensive, high-performance, fully-integrable, multi-standard transceiver, which suppresses spurious noise signals. The invention provides a topology that satisfies this need, using a first signal generator which produces an oscillator signal f1 and a second signal generator which produces a mono-tonal mixing signal ?2, where f1 is a multiple of the frequency of ?2; and a logic circuit for generating a multi-tonal mixing signal ?1, where ?1*?2 has significant power at the frequency of said local oscillator signal being emulated, neither of said cp1 nor said ?2 having significant power at the carrier frequency of said input signal x(t) or said LO signal being emulated.

Abstract: A method and system for dynamically shifting spurious tones away from the desired frequency in a virtual local oscillator receiver, such that any undesired signal residing at such spurious tones are effectively delineated from the desired signal and removed from the RF input signal. The system detects the presence of potential undesired blocker signals in the RF input signal, and initiates an iterative power comparison and mixer signal adjustment loop. As the virtual local oscillator uses two mixer signals, the frequency of one of the mixer signals is adjusted during the loop until the power of the down-converted signal is minimized to a predetermined level. Minimized power in the down-converted signal is indicative of the absence of the blocker signal, since the presence of a relatively high power signal is indicative of a blocker signal overlapping with a desired signal.

Abstract: A CMOS transconductor for cancelling third-order intermodulation is provided. The transconductor includes a transconductance circuit and a tuneable distortion circuit. The transconductance circuit takes an input voltage and generates an output current having a transconductance element and an IM3 element. The distortion circuit takes the same input voltage and generates a current having an IM3 element of equal amplitude and opposite phase to the IM3 element of the transconductance circuit. A controller circuit tunes the distortion circuit to adjust its IM3 element to substantially equal the amplitude of the IM3 of the transconductance circuit. The distortion and transconductance circuits are arranged to sum their output currents thereby effectively cancelling the IM3 elements, leaving the transconductance relatively unmodified.

Abstract: The present invention relates generally to communications, and more specifically to a method and apparatus for generating local oscillator signals used for up- and down-conversion of RF (radio frequency) signals. A major problem in the design of modulators and demodulators, if the leakage of local oscillator (LO) signals into the received signal path. The invention presents a number of highly integratable circuits which resolve the LO leakage problem, using regenerative divider circuits acting on oscillator signals which are running at a multiple or fraction of the frequency of the desired LO signal, to generate in-phase (I) and quadrature (Q) mixing signals. Embodiments of these circuits also use harmonic subtraction and polyphase mixers, as well as virtual local oscillator TM (VLO) mixing signals. VLO mixing signals are signal pairs which emulate local oscillator signals by means of complementary mono-tonal and multi-tonal mixing signals.

Abstract: A transceiver interface architecture where the same RF transceiver can be used in wireless devices that support any number of standards, with or without receive diversity implementation. Each input port of the RF transceiver can be shared by a number of input signals, which effectively expands the number of available input ports. Input port sharing can be realized with virtual ports that receive two or more input signals and selectively pass one signal to the physical input port. The use of virtual ports allows for flexible wireless design implementations using the same RF transceiver, and in particular, for receive diversity implementations that inherently require dedicated input ports. The use of low cost and small area virtual ports obviates the need for larger and more costly RF receivers.

Abstract: A system for generating a supply voltage, temperature and process compensated gain control voltage from a digital data word. In particular, the compensated gain voltage control voltage maintains a linear relationship between a change in gain in response to an input gain control voltage for a gain circuit of a transmitter circuit. A monitor circuit senses at least one of the supply voltage, temperature and process parameters, and generates a first set of digital signals corresponding to the sensed parameter. A digital compensator circuit converts the input gain control voltage into a second set of digital signals, and decodes the combined first and second set of digital signals to provide a data word. The data word is converted into an analog voltage representing the compensated gain voltage control voltage. The digital compensator circuit includes a table of compensation values, each accessible by a distinct combination of the first and second set of digital signals.