Patents by Inventor Takaaki Kawahara

Takaaki Kawahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9455264
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×1013 to 2×1014 atoms/cm2.
    Type: Grant
    Filed: July 1, 2015
    Date of Patent: September 27, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Tatsunori Kaneoka, Takaaki Kawahara
  • Publication number: 20150303205
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×1013 to 2×1014 atoms/cm2.
    Type: Application
    Filed: July 1, 2015
    Publication date: October 22, 2015
    Inventors: Tatsunori Kaneoka, Takaaki Kawahara
  • Patent number: 9105739
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×1013 to 2×1014 atoms/cm2.
    Type: Grant
    Filed: March 2, 2013
    Date of Patent: August 11, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsunori Kaneoka, Takaaki Kawahara
  • Publication number: 20130240977
    Abstract: A semiconductor device with a nonvolatile memory is provided which has improved electric performance. A memory gate electrode is formed over a semiconductor substrate via an insulating film. The insulating film is an insulating film having a charge storage portion therein, and includes a first silicon oxide film, a silicon nitride film over the first silicon oxide film, and a second silicon oxide film over the silicon nitride film. Metal elements exist between the silicon nitride film and the second silicon oxide film, or in the silicon nitride film at a surface density of 1×1013 to 2×1014 atoms/cm2.
    Type: Application
    Filed: March 2, 2013
    Publication date: September 19, 2013
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsunori Kaneoka, Takaaki Kawahara
  • Patent number: 8293632
    Abstract: To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Masaru Kadoshima, Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20120056268
    Abstract: There is provided a technology capable of achieving, in a semiconductor device having a MISFET using an insulating film containing hafnium as a gate insulating film, an improvement in the reliability of a MISFET. In the present invention, the gate insulating film of an n-channel core transistor is provided with a structure different from that of the gate insulating film of a p-channel core transistor. Specifically, in the n-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfZrSiON film is used. On the other hand, in the p-channel core transistor, as the gate insulating film thereof, a laminate film of a silicon oxide film and a HfSiON film is used.
    Type: Application
    Filed: July 26, 2011
    Publication date: March 8, 2012
    Inventors: Masaharu MIZUTANI, Masaru KADOSHIMA, Takaaki KAWAHARA, Masao INOUE, Hiroshi UMEDA
  • Publication number: 20120045876
    Abstract: There is provided a technology capable of preventing the increase in threshold voltages of n channel type MISFETs and p channel type MISFETs in a semiconductor device including CMISFETs having high dielectric constant gate insulation films and metal gate electrodes. When a rare earth element or aluminum is introduced into a Hf-containing insulation film which is a high dielectric constant gate insulation film for the purpose of adjusting the threshold value of the CMISFET, a threshold adjustment layer including a lanthanum film scarcely containing oxygen, and a threshold adjustment layer including an aluminum film scarcely containing oxygen are formed over the Hf-containing insulation film in an nMIS formation region and a pMIS formation region, respectively. This prevents oxygen from being diffused from the threshold adjustment layers into the Hf-containing insulation film and the main surface of a semiconductor substrate.
    Type: Application
    Filed: July 15, 2011
    Publication date: February 23, 2012
    Inventors: Takaaki KAWAHARA, Shinsuke Sakashita, Masaru Kadoshima, Hiroshi Umeda
  • Patent number: 8120118
    Abstract: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
    Type: Grant
    Filed: November 10, 2010
    Date of Patent: February 21, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20110284971
    Abstract: There are provided a semiconductor device in which the threshold voltage of a p-channel field effect transistor is reliably controlled to allow a desired characteristic to be obtained, and a manufacturing method thereof. As a heat treatment performed at a temperature of about 700 to 900° C. proceeds, in an element formation region, aluminum (Al) in an aluminum (Al) film is diffused into a hafnium oxynitride (HfON) film, and thereby added as an element to the hafnium oxynitride (HfON) film. In addition, aluminum (Al) and titanium (Ti) in a hard mask formed of a titanium aluminum nitride (TiAlN) film are diffused into the hafnium oxynitride (HfON) film, and thereby added as elements to the hafnium oxynitride (HfON) film.
    Type: Application
    Filed: May 17, 2011
    Publication date: November 24, 2011
    Inventors: Shinsuke SAKASHITA, Takaaki Kawahara, Masaru Kadoshima, Masao Inoue, Hiroshi Umeda
  • Publication number: 20110057265
    Abstract: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 10, 2011
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinsuke SAKASHITA, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20100320542
    Abstract: To improve the performance of a CMISFET having a high-k gate insulating film and a metal gate electrode. An n-channel MISFET has, over the surface of a p-type well of a semiconductor substrate, a gate electrode formed via a first Hf-containing insulating film serving as a gate insulating film, while a p-channel MISFET has, over the surface of an n-type well, another gate electrode formed via a second Hf-containing insulating film serving as a gate insulating film. These gate electrodes have a stack structure of a metal film and a silicon film thereover. The first Hf-containing insulating film is an insulating material film comprised of Hf, a rare earth element, Si, O, and N or comprised of Hf, a rare earth element, Si, and O, while the second Hf-containing insulating film is an insulating material film comprised of Hf, Al, O, and N or comprised of Hf, Al, and O.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 23, 2010
    Inventors: Takaaki Kawahara, Shinsuke Sakashita, Masaru Kadoshima
  • Patent number: 7855134
    Abstract: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: December 21, 2010
    Assignee: Renesas Electronics Corporation
    Inventors: Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20100279496
    Abstract: To improve productivity and performance of a CMISFET including a high-dielectric-constant gate insulating film and a metal gate electrode. An Hf-containing insulating film for a gate insulating film is formed over the main surface of a semiconductor substrate. A metal nitride film is formed on the insulating film. The metal nitride film in an nMIS formation region where an n-channel MISFET is to be formed is selectively removed by wet etching using a photoresist pattern on the metal nitride films a mask. Then, a threshold adjustment film containing a rare-earth element is formed. The Hf-containing insulating film in the nMIS formation region reacts with the threshold adjustment film by heat treatment. The Hf-containing insulating film in a pMIS formation region where a p-channel MISFET is to be formed does not react with the threshold adjustment film because of the existence of the metal nitride film.
    Type: Application
    Filed: April 6, 2010
    Publication date: November 4, 2010
    Inventors: Masaru KADOSHIMA, Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20090218634
    Abstract: Provided is a highly reliable semiconductor device equipped with a plurality of semiconductor elements having desired properties, respectively; and a manufacturing method facilitating the manufacture of the semiconductor device. The semiconductor device is manufactured by forming a gate-electrode metal film having a thickness of from 3 to 30 nm over the entire upper surface of a gate insulating film; forming an n-side cap layer having a thickness of 10 nm or less over the entire upper surface of a portion of the gate-electrode metal film belonging to an nFET region by using a material different from that of the gate-electrode metal film; and carrying out heat treatment over the n-side cap layer to diffuse the material of the n-side cap layer into the gate-electrode metal film immediately below the n-side cap layer and react them to form an n-side gate-electrode metal film in a nFET region. A poly-Si layer is then deposited, followed by gate electrode processing.
    Type: Application
    Filed: January 15, 2009
    Publication date: September 3, 2009
    Inventors: Shinsuke Sakashita, Takaaki Kawahara, Jiro Yugami
  • Publication number: 20080128833
    Abstract: A high-dielectric-constant film including hafnium, wherein the above-mentioned high-dielectric-constant film includes deuterium at a ratio higher than the ratio of deuterium to hydrogen present in nature. In a field-effect transistor provided with the high-dielectric-constant film including hafnium, the interface state density at the interface between a silicon substrate and a gate dielectric film decreases and carrier mobility in the gate dielectric film increases. In the present invention, a high-dielectric-constant constant second dielectric film, which is a thin film including hafnium such as HfSiON or HfAlOx and including deuterium at a ratio higher than the ratio of deuterium to hydrogen present in nature, is used as the gate dielectric film of the field-effect transistor.
    Type: Application
    Filed: August 25, 2005
    Publication date: June 5, 2008
    Inventors: Takaaki Kawahara, Kazuyoshi Torii, Minoru Inoue, Satoshi Hasaka
  • Publication number: 20080121999
    Abstract: The present invention offers the semiconductor device which can solve each problem, such as Fermi level pinning, formation of gate electrode depletion, and a diffusion phenomenon, can adopt a material suitable for each gate electrode of the MOS structure from which threshold voltage differs, and can adjust (control) threshold voltage appropriately by the manufacturing process simplified more and which has a MOS structure. In the semiconductor device which has a MOS structure concerning the present invention, a PMOS transistor has the structure in which the gate insulating film, first metal layer, second metal layer, and polysilicon layer was formed in the order concerned. An NMOS transistor has the structure by which a gate insulating film and polysilicon were formed in the order concerned.
    Type: Application
    Filed: July 2, 2007
    Publication date: May 29, 2008
    Applicant: Renesas Technology Corp.
    Inventors: Takaaki KAWAHARA, Shinsuke Sakashita, Jiro Yugami
  • Patent number: 7268047
    Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 11, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Patent number: 7087495
    Abstract: A method for manufacturing a semiconductor device includes forming a first insulating film on a substrate, forming a second insulating film on the first insulating film, and forming a gate electrode on the second insulating film. Forming the second insulating film includes supplying film-forming materials and adsorbing the film-forming materials on the first insulating film, purging the film-forming materials that have not been adsorbed, supplying oxidants to oxidize the adsorbed film-forming materials, and purging the oxidants that have not contributed to oxidization. Forming the second insulating film is repeated in cycles, continuously, and the purging time of the oxidants in an initial number of the cycles is longer than the purging time of the oxidants in cycles following the initial number of cycles.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: August 8, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Takaaki Kawahara, Kazuyoshi Torii
  • Publication number: 20060138572
    Abstract: A gate insulating film on a silicon substrate of includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Application
    Filed: February 21, 2006
    Publication date: June 29, 2006
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki
  • Patent number: 7034369
    Abstract: A gate insulating film on a silicon substrate includes a SiO2 film and a high-k film. The high-k film contains a transition metal, aluminum, silicon, and oxygen. The concentration of silicon in the high-k film is higher than the concentrations of the transition metal and aluminum in the vicinity of the interface with the SiO2 film and the vicinity of the interface with the gate electrode. Furthermore, it is preferable that the concentration of silicon is the highest at least in one of the vicinity of the interface with the SiO2 film or the vicinity of the interface with the gate electrode, gradually decreases with distance from these interfaces, and becomes the lowest in a central part of the high-k film.
    Type: Grant
    Filed: August 9, 2004
    Date of Patent: April 25, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsunetoshi Arikado, Takaaki Kawahara, Kazuyoshi Torii, Hiroshi Kitajima, Seiichi Miyazaki