Patents by Inventor Takaharu Tanaka

Takaharu Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240124821
    Abstract: A culture vessel includes at least a first port used for medium supply and a second port used for medium discharge, and A medium supplying vessel serves as a mixing vessel for adjusting a concentration of A new medium to be supplied to the culture vessel. A cell culture method includes: transferring a portion of a used medium in the culture vessel from the culture vessel to the mixing vessel; creating a concentration-adjusted medium by mixing the new medium and the portion of the used medium in the mixing vessel; and filling the culture vessel with the concentration-adjusted medium by discharging a remaining used medium from the culture vessel while the concentration-adjusted medium is transferred from the mixing vessel to the culture vessel.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventors: Takaharu NISHIYAMA, Satoshi TANAKA, Osamu KOSEKI, Takahiko TOTANI
  • Patent number: 11952344
    Abstract: Provided is a heterocyclic compound that can have an antagonistic action on an NMD A receptor containing the NR2B subunit and that is expected to be useful as a prophylactic or therapeutic agent for depression, bipolar disorder, migraine, pain, peripheral symptoms of dementia and the like. A compound represented by the formula (I), wherein each symbol is as defined in the DESCRIPTION, or a salt thereof.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: April 9, 2024
    Assignee: Takeda Pharmaceutical Company Limited
    Inventors: Yuya Oguro, Makoto Kamata, Shuhei Ikeda, Takeshi Wakabayashi, Norihito Tokunaga, Taku Kamei, Mitsuhiro Ito, Shigemitsu Matsumoto, Hirotaka Kamitani, Takaharu Hirayama, Toshio Tanaka, Hiroshi Banno, Nobuyuki Takakura, Jinichi Yonemori, Takuya Fujimoto
  • Patent number: 11941965
    Abstract: An object of the present disclosure is to enable a warning to be issued to a person who is highly likely to be put in danger at a risky point. In an information processing apparatus, a controller acquires information indicating a risky point, acquires a state of a person with a predetermined positional relationship to the risky point, and determines whether or not the state of the person is a state where there is a high possibility of being put in danger, among a plurality of states of the person assumable at the risky point. Furthermore, in a case where the state of the person is determined to be the state where there is a high possibility of being put in danger, the controller causes an output unit to output information indicating a warning.
    Type: Grant
    Filed: August 4, 2021
    Date of Patent: March 26, 2024
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventors: Yurika Tanaka, Shuichi Sawada, Takaharu Ueno, Shin Sakurada, Daiki Yokoyama, Genshi Kuno
  • Publication number: 20240076603
    Abstract: Provided is a cell culture system capable of detecting a proliferative property of cells in a culture vessel at a desired timing during a culture when the cells are statically cultured in the culture vessel formed of a gas permeable member. A cell culture system is a system for statically culturing cells with a culture vessel at least partially formed of a gas permeable member. The cell culture system includes an oxygen concentration sensor that measures an oxygen concentration in a vicinity of a culture surface inside the culture vessel, and a proliferation detection unit that detects a proliferative property of the cells based on an oxygen permeability of the gas permeable member, a measurement value of the oxygen concentration sensor, an oxygen concentration around the culture vessel, and an oxygen consumption per cell of the cells.
    Type: Application
    Filed: April 27, 2023
    Publication date: March 7, 2024
    Inventors: Osamu KOSEKI, Satoshi TANAKA, Takahiko TOTANI, Yosuke MATSUOKA, Takaharu NISHIYAMA
  • Publication number: 20230270574
    Abstract: Disclosed is an intravascular indwelling stent that include a stent main body and a polymer film covering the stent main body. Through-holes are formed in the polymer film. The through-holes connect an inside and an outside of a cylinder of the intravascular indwelling stent to each other and each have an opening size of 0.02 mm or more and 0.2 mm or less. An opening occupancy, which is the ratio of the opening area of all the through-holes included in a unit area of the outer surface of the polymer film to the unit area, is 25% or more and 41% or less. A surface density of boundary, which is the ratio of the length of opening edges of all the through-holes included in a unit area of the outer surface of the polymer film to the unit area, is 9.5/mm or more and 30/mm or less.
    Type: Application
    Filed: July 15, 2021
    Publication date: August 31, 2023
    Applicant: BIOTUBE CO., LTD
    Inventors: Yasuhide NAKAYAMA, Hisashi SUGIURA, Takaharu TANAKA
  • Patent number: 10779973
    Abstract: A stent includes a cylindrical main body portion, a linkage portion, and a marker attachment portion. The main body portion extends in an axial direction. The linkage portion extends from an end of the main body portion in the axial direction. The marker attachment portion is linked to the main body portion through the linkage portion. The linkage portion includes a bent portion tilting the marker attachment portion outward in a radial direction of the main body portion.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: September 22, 2020
    Assignee: GOODMAN CO., LTD.
    Inventors: Takaharu Tanaka, Yumiko Nomura
  • Publication number: 20170367856
    Abstract: A stent includes a cylindrical main body portion, a linkage portion, and a marker attachment portion. The main body portion extends in an axial direction. The linkage portion extends from an end of the main body portion in the axial direction. The marker attachment portion is linked to the main body portion through the linkage portion. The linkage portion includes a bent portion tilting the marker attachment portion outward in a radial direction of the main body portion.
    Type: Application
    Filed: September 8, 2017
    Publication date: December 28, 2017
    Applicant: GOODMAN CO., LTD.
    Inventors: Takaharu Tanaka, Yumiko Nomura
  • Patent number: 9489139
    Abstract: A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: November 8, 2016
    Assignee: SOCIONEXT INC.
    Inventors: Nobuyuki Ichiguchi, Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Publication number: 20160048330
    Abstract: A command processing apparatus that processes a plurality of commands which are issued independently from a first master and a second master is provided. The command processing apparatus sequentially issues commands to a storage apparatus including a plurality of banks. The first master issues a first command and a second command in order to the command processing apparatus, with the first command being a command to request access to a first bank and the second command being a command to request access to a second bank different from the first bank. When the second master issues a third command to the command processing apparatus during an interval between issuance of the first command and the second command, the command processing apparatus issues the second command to the storage apparatus consecutively after the first command by prioritizing the second command over the third command.
    Type: Application
    Filed: October 28, 2015
    Publication date: February 18, 2016
    Applicant: Socionext Inc.
    Inventors: Nobuyuki ICHIGUCHI, Tetsuji MOCHIDA, Ryuta NAKANISHI, Takaharu TANAKA
  • Patent number: 9201819
    Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: December 1, 2015
    Assignee: SOCIONEXT INC.
    Inventors: Nobuyuki Ichiguchi, Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Patent number: 7904666
    Abstract: In a device, in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. When the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.
    Type: Grant
    Filed: July 6, 2006
    Date of Patent: March 8, 2011
    Assignee: Panasonic Corporation
    Inventors: Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Patent number: 7852343
    Abstract: The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m?M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n?N, become successive.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: December 14, 2010
    Assignee: Panasonic Corporation
    Inventors: Takaharu Tanaka, Tetsuji Mochida, Nobuyuki Ichiguchi
  • Publication number: 20100198965
    Abstract: In order to easily ensure service quality by reducing network traffic, a network monitoring section (30) monitors a transfer rate (bit rate, bandwidth) of data which is transferred between each of the network-enabled devices connected through a LAN (100) and interne (110), and outputs the transfer rate, that is, network load information representing a network load, to a network QoS control section (31). The network QoS control section (31) determines whether a transfer is possible or not (whether a requested transfer rate is available or not) based on the network load information and the requested transfer rate requested from the network-enabled devices, etc.; and if it is determined that the requested transfer rate is not available, reduces an image in the transferred data in size; then, the data of reduced image is transferred. Thus, the transfer rate can be kept low.
    Type: Application
    Filed: June 20, 2008
    Publication date: August 5, 2010
    Inventor: Takaharu Tanaka
  • Publication number: 20090327571
    Abstract: A command processing apparatus and method are provided for optimally processing commands issued asynchronously from a plurality of masters to a storage apparatus including a plurality of banks, where each master issues commands for a bank 0 and a bank 1 alternately. The command processing apparatus includes buffer units that obtain commands issued from the plurality of masters, an arbitration unit that arbitrates the obtained commands, and an issuance unit that issues commands to the storage apparatus according to the arbitration. The arbitration unit reads the commands of the plurality of masters obtained in the buffer units, and selects one command as a result of arbitration. The arbitration unit waits until a next command of a master relating to the selected command becomes readable, and reads the next command. The issuance unit consecutively issues the selected command and the read command to the storage apparatus.
    Type: Application
    Filed: July 28, 2006
    Publication date: December 31, 2009
    Applicant: PANASONIC CORPORATION
    Inventors: Nobuyuki Ichiguchi, Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Publication number: 20090313441
    Abstract: In a device in which a master that requires access at a predetermined rate and a processor that requires responsiveness to an access request access a shared memory, responsiveness to the access request of the processor is improved while the access of the master at the predetermined rate is guaranteed, compared to conventional technologies. When the master has a resource available for accessing the shared memory, the master accesses the shared memory at the predetermined rate or above. In a case that the access is executed at the predetermined rate or above, the processor accesses the shared memory by using a resource that was originally allocated to the master.
    Type: Application
    Filed: July 6, 2006
    Publication date: December 17, 2009
    Inventors: Tetsuji Mochida, Ryuta Nakanishi, Takaharu Tanaka
  • Publication number: 20090235003
    Abstract: Access requests issued from access circuits 30, 40 are arbitrated in an arbitration circuit 20 and are accessed to a storage device 10. On the other hand, access requests issued from the access circuits 30, 40 are arbitrated in the arbitration circuit 21 and are accessed to a storage device 11.
    Type: Application
    Filed: December 26, 2005
    Publication date: September 17, 2009
    Inventors: Takaharu Tanaka, Tetsuji Mochida
  • Publication number: 20070208919
    Abstract: The information processing device in the present invention includes a memory 1 which is a DRAM featuring a burst mode, and burst-transfers data at successive column addresses, masters (13), (14), and (15) which issue access requests, and a command processing unit (11) which converts an access address that is included in the access request issued from each master. One or more of the masters access an M×N rectangular area where M and N are integers, and the command processing unit (11) converts access addresses so that a column address of data at the (K+m)th column, where K and m are integers and m?M, of an Lth line, and a column address of data at a Kth column of an (L+n)th line, where L and n are integers and n?N, become successive.
    Type: Application
    Filed: March 18, 2005
    Publication date: September 6, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Takaharu Tanaka, Tetsuji Mochida, Nobuyuki Ichiguchi
  • Patent number: 6987811
    Abstract: The speed of decoding processing for variable-length coded image data is improved.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: January 17, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Takaharu Tanaka, Hideshi Nishida, Kosuke Yoshioka, Tokuzo Kiyohara
  • Patent number: 6470376
    Abstract: The counter 52 is set with an initial value of “1” and is a counter with a maximum value of “4”. This counter 52 increments the count value held by the flip-flop 51 in synchronization with a clock signal so that the count value changes as shown by the progression 1,2,3,4,1,2,3,4. This clock signal is also used by the instruction decode control unit 11 to control the execution of instructions, with the counting by the counter 52 being performed once for each instruction execution performed by the instruction decode control unit 11. The comparator 54 compares the count value counted by the counter 52 with the maximum value “4”, and when the values match, sets the task switching signal chg_task_ex at a “High” value, so that the processing switches to the execution of the next task.
    Type: Grant
    Filed: March 3, 1998
    Date of Patent: October 22, 2002
    Assignee: Matsushita Electric Industrial Co., LTD
    Inventors: Takaharu Tanaka, Kiyoshi Maenobu, Kosuke Yoshioka, Makoto Hirai, Tokuzo Kiyohara
  • Patent number: D967408
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: October 18, 2022
    Inventors: Takaharu Tanaka, Hisashi Sugiura, Etsuko Hirota, Yasuhiko Kato, Motoki Asai