Patents by Inventor Takaharu Yamano

Takaharu Yamano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7459343
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method comprises a first step of grinding a second principle surface of a semiconductor substrate opposite to a first principle surface of the semiconductor substrate on which semiconductor device elements are formed, a second step of attaching a support structure configured to support the semiconductor substrate to the second principle surface after the first step, and a third step of detaching the semiconductor substrate from the support structure.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: December 2, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20080290491
    Abstract: In a stacked layer type semiconductor package constructed by stacking a plurality of packages with each other, the plurality of packages include a semiconductor package including: a semiconductor chip; a substrate in which a concave portion has been formed, the semiconductor chip being mounted in the concave portion; and a wiring line structure constructed in such a manner that the wiring line structure can be externally connected to the semiconductor chip at least just above and just under the semiconductor chip.
    Type: Application
    Filed: October 23, 2007
    Publication date: November 27, 2008
    Inventors: Takaharu Yamano, Tsuyoshi Kobayashi
  • Publication number: 20080261396
    Abstract: A disclosed substrate is composed of a base member having a through-hole, a penetrating via provided in the through-hole, and a wiring connected to the penetrating via. The penetrating via includes a penetrating part having two ends on both sides of the base member, which is provided in the through-hole, a first protrusion protruding from the base member, which is formed on a first end of the penetrating part so as to be connected to the wiring, and a second protrusion protruding from the base member, which is formed on a second end of the penetrating part. The first protrusion and second protrusion are wider than a diameter of the through-hole.
    Type: Application
    Filed: April 3, 2008
    Publication date: October 23, 2008
    Inventor: Takaharu YAMANO
  • Publication number: 20080230921
    Abstract: A semiconductor device includes a first semiconductor chip; a multilayer wiring which is formed on the first semiconductor chip and which is connected to the first semiconductor chip; a second semiconductor chip connected to the first semiconductor chip by way of the multilayer wiring; a sealing material which seals the second semiconductor chip; and projecting plugs which are connected to the multilayer wiring and whose extremities become exposed on the sealing material.
    Type: Application
    Filed: October 2, 2007
    Publication date: September 25, 2008
    Inventor: Takaharu Yamano
  • Patent number: 7417311
    Abstract: A semiconductor wafer is thinned to a predetermined thickness by grinding the backside thereof (which is opposite to the side where a plurality of devices are formed and metal posts are further formed), and then a metal layer made of metal having a linear thermal expansion coefficient close to that of the semiconductor wafer is formed on the ground side. Further, the semiconductor wafer is sealed with resin, metal bumps are bonded to the tops of the metal posts (barrier metal layer), and then the semiconductor wafer is divided into the respective semiconductor devices. Silicon is used as material for the semiconductor wafer, and tungsten or molybdenum is used as metal constituting the metal layer.
    Type: Grant
    Filed: November 16, 2004
    Date of Patent: August 26, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20080128917
    Abstract: It is a semiconductor device that has a semiconductor chip on which an electrode pad is formed, an electric connection member formed on the electrode pad, an insulating layer formed on the semiconductor chip, and an electrically conductive pattern connected to the electric connection member. An opening portion corresponding to the electric connection member is formed in the conductive pattern. The conductive pattern is electrically connected to the electric connection member by an electrically conducting paste embedded in the opening portion.
    Type: Application
    Filed: November 20, 2007
    Publication date: June 5, 2008
    Inventor: Takaharu Yamano
  • Patent number: 7378732
    Abstract: A plurality of semiconductor packages is collectively fabricated on a wafer in a batch process and the wafer is then diced to obtain discrete semiconductor packages. The semiconductor package is a stacked body formed by bonding two or more semiconductor devices. Each semiconductor device comprises a substrate and a device pattern formed on a surface of the substrate. The semiconductor devices are stacked in such a fashion that a device pattern surface of the lower semiconductor device faces a non-device pattern surface of the semiconductor device stacked on the same.
    Type: Grant
    Filed: April 12, 2004
    Date of Patent: May 27, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Takako Yoshihara, Masahiro Sunohara
  • Patent number: 7370411
    Abstract: A method of manufacturing a wiring board includes: forming a first insulating layer on a supporting board; mounting at least one reinforcing member on the first insulating layer; mounting at least one semiconductor chip on the first insulating layer; forming a second insulating layer on the reinforcing member and the semiconductor chip; and forming a wiring on the second insulating layer, the wiring being connected to the semiconductor chip.
    Type: Grant
    Filed: March 10, 2006
    Date of Patent: May 13, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Patent number: 7365436
    Abstract: A disclosed substrate includes a base member having a through-hole, and a conductive metal filling in the through-hole so as to form a penetrating via. The penetrating via contains a conductive core member that is substantially at the central axis of the through-hole.
    Type: Grant
    Filed: October 11, 2005
    Date of Patent: April 29, 2008
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20080089048
    Abstract: A substrate with built-in electronic components includes a substrate on which a first conductive pattern is formed; an electronic component mounted on the substrate; an insulting layer which is formed by stacking a plurality of resin layers including indifferent additive ratios an additive material for adjusting hardness; a second conductive pattern formed on the insulating layer; and a conductive post for connecting the first conductive pattern to the second conductive pattern.
    Type: Application
    Filed: October 10, 2007
    Publication date: April 17, 2008
    Inventors: Takaharu Yamano, Yoshihiro Machida
  • Publication number: 20080076207
    Abstract: The present invention relates to a manufacturing method of a semiconductor device having a size approximately same as the size of a semiconductor chip when viewed in a plan view, in which the semiconductor chip is flip-chip bonded to a wiring pattern, and an object of the invention is to provide the manufacturing method of a semiconductor device which allows reduction in the number of process steps to realize the minimization of manufacturing cost. An insulating resin 13 is formed so as to cover a plurality of internal connection terminals 12 and a surface of a plurality of semiconductor chips 11 on which the plurality of internal connection terminals are provided, then a metal layer 33 for forming a wiring pattern is formed over the insulating resin 13, and by pressing the metal layer 33, the metal layer 33 and the plurality of internal connection terminals 12 are pressure-bonded.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 27, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Takaharu Yamano, Tadashi Arai
  • Publication number: 20080073798
    Abstract: The present invention relates to a semiconductor device including a semiconductor chip encapsulated by an encapsulation resin and a manufacturing method thereof, and an object of the invention is to provide the semiconductor chip and its manufacturing method in which the reduction in size may be attempted. It includes a semiconductor chip 15, an external connection terminal pad 18 electrically connected to the semiconductor chip 15, and an encapsulation resin 16 encapsulating the semiconductor chip 15, wherein a wiring pattern 12 on which the external connection terminal pad 18 is formed is provided between the semiconductor chip 15 and the external connection terminal pad 18, and the semiconductor chip 15 is flip-chip bonded to the wiring pattern 12.
    Type: Application
    Filed: September 17, 2007
    Publication date: March 27, 2008
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventor: Takaharu Yamano
  • Patent number: 7312536
    Abstract: A disclosed substrate having a built-in semiconductor chip includes the built-in semiconductor chip, a resin member having the built-in semiconductor chip contained therein and external connection terminals. The resin member contains a resin and 60 to 90% by weight of spherical filler.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: December 25, 2007
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Tadashi Arai, Yoshihiro Machida
  • Patent number: 7288841
    Abstract: A laminated semiconductor package includes: a first package having: an insulating layer; a first semiconductor chip embedded in the insulating layer; a wiring connected to the first semiconductor chip; a first connecting section which is formed on a first face side of the insulating layer and connected to the wiring; and a second connecting section which is formed on a second face side of the insulating layer and connected to the wiring, the second face side being opposite to the first face side; and a second package having: a second semiconductor chip; and a third connecting section connected to the second semiconductor chip. In the laminated semiconductor chip, the first package and the second package are laminated one on the other, and the second connecting section and the third connecting section are connected to each other.
    Type: Grant
    Filed: June 12, 2006
    Date of Patent: October 30, 2007
    Assignee: Shinko Electric Industries, Co., Ltd.
    Inventor: Takaharu Yamano
  • Publication number: 20070224809
    Abstract: Resist films 19 for liftoff are formed on an insulating layer 12 corresponding to a wiring formation region A so as to expose the insulating layer 12 corresponding to formation positions of first seed layers 14 and thereafter, metal films 21 are formed. Then, the resist films 19 for liftoff are removed and the first and second seed layers 14, 22 are formed. Thereafter, conductive metals 15 are precipitated and grown on the first seed layers 14 by an electrolytic plating method and thereafter the second seed layers 22 are removed and thereby, wirings 13 made of the first seed layers 14 and the conductive metals 15 are formed.
    Type: Application
    Filed: February 27, 2007
    Publication date: September 27, 2007
    Inventor: Takaharu Yamano
  • Patent number: 7250329
    Abstract: A method of fabricating a built-in chip type substrate containing a semiconductor chip is disclosed. The method comprises a first step of mounting the semiconductor chip on a substrate; a second step of forming chip connection wiring connected to the semiconductor chip mounted on the substrate; and a step of forming an alignment post on the substrate before the first step, the alignment post being used for positioning the chip connection wiring.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: July 31, 2007
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Takaharu Yamano, Tadashi Arai
  • Publication number: 20070052071
    Abstract: It is configured to comprise a semiconductor chip 110, a resin member 106 for forming a cavity 109 in which this semiconductor chip 110 is installed, and wiring 105 constructed of pattern wiring 105b formed so as to be exposed to a lower surface 106a of this resin member 106 and also connected to the semiconductor chip 110 and a post part 105a in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to a front surface 106b of the resin member 106.
    Type: Application
    Filed: September 6, 2006
    Publication date: March 8, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano
  • Publication number: 20070051459
    Abstract: The method for forming wiring includes: laminating a thermosetting resin film in a semi-cured state and a metallic foil in this order on an insulating substrate where base-layer wiring is formed, a mat surface of the metallic foil facing the resin film, pressing the film and the foil with application of heat; forming an opening in the metallic foil so as to expose a part of the insulating resin layer in which a via hole is to be formed; forming the via hole in the insulating resin layer by irradiating high-energy beams on to insulating resin layer by using as a mask the metallic foil in which the opening is formed; performing a desmear process of the via hole via the opening of the metallic foil; removing the metallic foil by etching; forming an electroless-plated layer that continuously covers the top surface of the insulating resin layer, a side surface of the via hole and a top surface of the base-layer wiring corresponding to the bottom of the via hole; and forming wiring including an electroplated layer
    Type: Application
    Filed: September 7, 2006
    Publication date: March 8, 2007
    Inventors: Takaharu Yamano, Kosaku Harayama, Hiroyuki Kato, Tetsuya Koyama
  • Publication number: 20070052083
    Abstract: A semiconductor package 100 is constructed of a semiconductor chip 110, a sealing resin 106 for sealing this semiconductor chip 110, and wiring 105 formed inside the sealing resin 106. And, the wiring 105 is constructed of pattern wiring 105b connected to the semiconductor chip 110 and also formed so as to be exposed to a lower surface 106b of the sealing resin 106, and a post part 105a formed so as to extend in a thickness direction of the sealing resin 106, the post part in which one end is connected to the pattern wiring 105b and also the other end is formed so as to be exposed to an upper surface 106a of the sealing resin 106.
    Type: Application
    Filed: August 17, 2006
    Publication date: March 8, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Tsuyoshi Kobayashi, Tetsuya Koyama, Takaharu Yamano
  • Publication number: 20070045811
    Abstract: The laminated product in a structure including a glass-cloth contained resin layer according to this invention is a laminated product in which a wiring layer and an insulating layer alternately laminated are included and different wiring layers are electrically connected to each other by a via hole passing through the insulating layer, characterized in that at least one insulating layer 11 is formed of a laminated body including an insulating resin layer 7 on a lower wiring layer 5 and a glass-cloth contained resin layer 9 thereon, and in the laminated body, a via hole 17 continuously passes through from the upper glass-cloth contained resin layer 9 to the lower insulating resin layer 7.
    Type: Application
    Filed: August 8, 2006
    Publication date: March 1, 2007
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yoshihiro Machida, Kosaku Harayama, Takaharu Yamano