Patents by Inventor Takahide Ikeda

Takahide Ikeda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11187238
    Abstract: A propeller fan includes a cylindrical shaft portion provided on a rotation axis of the propeller fan; a plurality of blades provided on an outer peripheral side of the shaft portion; a connection portion provided adjacent to the shaft portion and connecting two of the plurality of blades that are adjacent to each other in a circumferential direction of the propeller fan; a first rib provided on at least one of a pressure surface of each of the plurality of blades and a surface of part of the connection portion that is located on a downstream side in the flow of air, and a second rib provided on at least one of a negative-pressure surface of each of the plurality of blades and a surface of part of the connection portion that is located on an upstream side in the flow of air.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 30, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Katsuyuki Yamamoto, Takuya Teramoto, Takahide Tadokoro, Hiroya Ito, Yuki Ugajin, Shingo Hamada, Takashi Ikeda, Takafumi Abe
  • Patent number: 11187239
    Abstract: A propeller fan according to an embodiment of the present invention includes a shaft provided a rotation axis of the propeller fan, and a blade provided on an outer peripheral side of the shaft. The blade has a trailing edge on a rear side of the blade in a rotation direction of the propeller fan. The trailing edge includes a first trailing edge located on an innermost side of the trailing edge, and a second trailing edge adjacent to and outward of the first trailing edge. Where an innermost point of the first trailing edge is a first connection point, a connection point between the first trailing edge and the second trailing edge is a second connection point, and a straight line that extends through the rotation axis and the first connection point is a reference line, the second connection point is located forward of the reference line in the rotation direction, or located on the reference line, and the second trailing edge is located rearward of the second connection point in the rotation direction.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: November 30, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takahide Tadokoro, Takuya Teramoto, Katsuyuki Yamamoto, Hiroya Ito, Yuki Ugajin, Shingo Hamada, Takashi Ikeda, Takafumi Abe
  • Patent number: 7238582
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: July 3, 2007
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20050101097
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Application
    Filed: December 1, 2004
    Publication date: May 12, 2005
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6864559
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: March 4, 2003
    Date of Patent: March 8, 2005
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6835632
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: June 13, 2003
    Date of Patent: December 28, 2004
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6740958
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: May 25, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6727152
    Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.
    Type: Grant
    Filed: February 28, 2002
    Date of Patent: April 27, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi
  • Publication number: 20030207544
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline silicon layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Application
    Filed: June 13, 2003
    Publication date: November 6, 2003
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20030178699
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: March 4, 2003
    Publication date: September 25, 2003
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6610569
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the polycrystalline first silicon layer has a positive in temperature dependence of resist while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: August 28, 2000
    Date of Patent: August 26, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Co., Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6524924
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistances while the second polycrystalline layer has a negative temperature dependance of resistance, or vise versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: February 25, 2003
    Assignees: Hitachi, Ltd., Hitachi Device Engineering
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Publication number: 20020153591
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Application
    Filed: April 4, 2002
    Publication date: October 24, 2002
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Publication number: 20020096718
    Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.
    Type: Application
    Filed: February 28, 2002
    Publication date: July 25, 2002
    Inventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi
  • Patent number: 6392277
    Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: May 21, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi
  • Patent number: 6208010
    Abstract: Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: March 27, 2001
    Assignee: Hitachi, Ltd.
    Inventors: Shinji Nakazato, Hideaki Uchida, Yoshikazu Saito, Masahiro Yamamura, Yutaka Kobayashi, Takahide Ikeda, Ryoichi Hori, Goro Kitsukawa, Kiyoo Itoh, Nobuo Tanba, Takao Watanabe, Katsuhiro Shimohigashi, Noriyuki Homma
  • Patent number: 6133094
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: October 17, 2000
    Assignees: Hitachi Ltd, Hitachi Device Engineering Co.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 6063686
    Abstract: A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: May 16, 2000
    Inventors: Hiroo Masuda, Hisako Sato, Takahide Nakamura, Katsumi Tsuneno, Kimiko Aoyama, Takahide Ikeda, Nobuyoshi Natsuaki, Shinichiro Mitani
  • Patent number: 5793097
    Abstract: The present invention provides a polycrystalline silicon conducting structure (e.g., a resistor) whose resistance value is controlled, and can be less variable and less dependent on temperature with respect to any resistant value, and a process of producing the same. Use is made of at least a two-layer structure including a first polycrystalline silicon layer of large crystal grain size and a second polycrystalline silicon layer of small crystal grain size, and the first polycrystalline silicon layer has a positive temperature dependence of resistance while the second polycrystalline layer has a negative temperature dependence of resistance, or vice versa. Moreover, the polycrystalline silicon layer of large grain size can be formed by high dose ion implantation and annealing, or by depositing the layers by chemical vapor deposition at different temperatures so as to form large-grain and small-grain layers.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: August 11, 1998
    Assignees: Hitachi, Ltd., Hitachi Device Engineering Company, Ltd.
    Inventors: Hiromi Shimamoto, Takashi Uchino, Takeo Shiba, Kazuhiro Ohnishi, Yoichi Tamaki, Takashi Kobayashi, Toshiyuki Kikuchi, Takahide Ikeda
  • Patent number: 5726488
    Abstract: A semiconductor device has a well region formed in the surface of a substrate, and has functional portions such as MOSFET and bipolar transistor formed in the well region. The carrier concentration profile of the well region assumes the shape of a valley in the direction of depth thereof, and a minimum point thereof has a concentration of smaller than 5.times.10.sup.15 cm.sup.-3 and is located at a position within 1.6 .mu.m from the surface of the substrate. Preferably, the minimum point should have a concentration of greater than 5.times.10.sup.14 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3, and more preferably a concentration of greater than 1.times.10.sup.15 cm.sup.-3 but smaller than 5.times.10.sup.15 cm.sup.-3.
    Type: Grant
    Filed: May 16, 1994
    Date of Patent: March 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Atsuo Watanabe, Yoshiaki Yazawa, Atsushi Hiraishi, Masataka Minami, Takahiro Nagano, Takahide Ikeda, Naohiro Momma