Abstract: A non-transitory computer-readable recording medium stores a conversion program for causing a computer to execute a process including: dividing a source program into a plurality of program blocks; selecting, based on a result of analysis of an access count from each of the plurality of program blocks to each of a plurality of accelerators, a first program block among the plurality of program blocks and an accelerator of an arrangement destination of the first program block, among the plurality of accelerators; and converting the first program block into a hardware logic to be operated in the accelerator of the arrangement destination.

Abstract: A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Abstract: A computer-readable recording medium stores a control program for causing a computer configured to execute scheduling of a job across a plurality of pieces of hardware deployed at a plurality of sites to execute a process. The process includes acquiring software information on a plurality of tasks included in the job, hardware information on the plurality of pieces of hardware, and site information on the plurality of sites, and determining which task of the job that has been input is to be allocated to which piece of hardware by using a result of machine learning based on the software information, the hardware information, and the site information that have been acquired.

Abstract: A semiconductor device includes: a first cache that includes a first memory and rewrite flags that indicate whether rewriting has been performed for each piece of data held in the first memory; and a second cache that includes a second memory and a third memory that has a lower writing speed than the second memory, stores data evicted from the first cache in the second memory when a rewrite flag corresponding to the evicted data indicates a rewrite state, and stores data evicted from the first cache in the third memory when a rewrite flag corresponding to the evicted data indicates a non-rewrite state.

Abstract: A non-transitory computer-readable recording medium stores a program for causing a computer to execute a process including estimating a usage period based on a user's usage status for each device in a system that provides a service at metered charge for the devices, calculating a first cost related to renewal of each device based on the estimated usage period, estimating a maintenance timing of each device from a failure history of each device, calculating a second cost related to maintenance of each device based on the maintenance timing of each device and the estimated usage period, generating a service cost of the service for each device, the service cost including the first cost and the second cost, and selecting a device to be used for the service based on the service cost generated for each device.

Abstract: A non-transitory computer-readable recording medium stores a program that causes a computer to execute a process that includes receiving load arrangement of jobs in a case where a compute server mounted in a compute rack in a server room executes the jobs, the server room being a room where the compute rack in which the compute server is mounted and a storage rack in which a storage is mounted are arranged, and estimating a time at which a predetermined job of the compute server is to be offloaded to the storage that generates less heat than the compute server and estimating setting temperature and an air volume of an air conditioner, based on the load arrangement and time-series data of temperature and power of the server room, such that the power of the server room is reduced within limitation conditions of the compute server, the storage, and the air conditioner.

Abstract: An arithmetic processing device that executes a single instruction/multiple data (SIMD) operation, includes a memory; and a processor coupled to the memory and configured to register an indefinite cycle instruction of a plurality of instructions to a first queue, register other instructions other than the indefinite cycle instruction of the plurality of instructions to a second queue, issue the indefinite cycle instruction registered to the first queue, and issue the other instructions registered to the second queue after issuing the indefinite cycle instruction.

Abstract: A device including: a processor executing a program; a first cache memory; a second cache memory belonging to a memory hierarchy lower than that of the first cache memory; a determination unit that determines, based on first information indicating a virtual address of information accessed in the second cache memory when the program is executed, second information indicating a virtual address of target information to be prefetched; and a prefetch unit that prefetches the target information and stores the prefetched target information in the second cache memory, wherein the second cache memory includes a conversion unit that converts, by using correspondence information indicating a correspondence relationship between the physical address of the target information and the virtual address of the target information, the second information into third information indicating a physical address of the target information, and the prefetch unit prefetches the target information using the third information.

Abstract: An information processing apparatus includes: an arithmetic processing unit that includes: a processor that executes a program; and a cache memory coupled to the processor, wherein the cache memory includes: an acquisition unit that acquires a physical address of target information that is a target of an event that has occurred in the cache memory when the program is executed; and a generation unit that converts the physical address of the target information into a virtual address of the target information by using correspondence information that indicates correspondence between the physical address of the target information and the virtual address of the target information, and generates log information in which virtual address information that indicates the virtual address of the target information and identification information of the event are associated with each other.

Abstract: A process includes extracting a first set of data to be used for construction of a first-model that outputs an estimated-value of first data at a first time that follows second times with respect to an input of a second set of data that includes second data that has been measured at the second times, from third sets of data that include third data that had been measured at third times prior to the second times, based on the second set, determining whether a second-model that has been previously constructed is identical to the first-model, based on the first set and one of the second set and the third sets used for the construction of the second-model, and when it is determined that the second-model is identical to the first model, acquiring the estimated-value output from the second-model by inputting the second set to the second-model.

Abstract: Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

Abstract: A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

Abstract: Designation of observation points in an observation target circuit for which operations are observed in simulation is accepted, and circuit data of an observation circuit is attached to circuit data of the observation target circuit so that the observation circuit is connected to the observation target circuit according to designation data of the observation points. At this time, a double-buffer configuration is adopted for the observation circuit, and the number of occurrence times of a specific state at a specific observation point during a first period and the number of occurrence times of the specific state at the specific observation point during a second period are alternately outputted and stored into RAM.

Abstract: A single module includes a shared combinational circuit, a multiplexed sequential circuit, and a common I/F and is substituted for a multiplexed module formed of plural modules of an identical category and type and including plural CPUs. Specifically, the shared combinational circuit is substituted for n combinational circuits, the multiplexed sequential circuit is substituted for n sequential circuits, and the common I/F is substituted for n input pins and n output pins.

Abstract: An apparatus for designing the layout of a circuit includes an acquiring unit, a determining unit, a specifying unit, an arranging unit, a modifying unit, and a routing unit. Based on net information acquired by the acquiring unit, the determining unit determines a wiring block of signal paths connecting cells connected through adjacent. The arranging unit arranges a wiring area between the cells that extends along user-specified reference points or user-specified reference segments received by the specifying unit. The modifying unit modifies the arranged wiring area and the routing unit routes the signal paths of the wiring block in the modified wiring area.