Patents by Inventor Takahiko Konishi

Takahiko Konishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6703686
    Abstract: An n-type low impurity concentration semiconductor layer is provided, by epitaxial growth or the like, on a p-type semiconductor substrate. In order to vertically form a semiconductor device in the low impurity concentration semiconductor layer, at least a p-type diffusion region is provided. In a surface of the semiconductor layer, a collector electrode and a base electrode are respectively formed in electrical connection to the n-type low impurity concentration semiconductor layer and the p-type diffusion region. The collector electrode is formed on a surface of the n+-type low resistance region of a polycrystal semiconductor formed depthwise in the low impurity concentration semiconductor layer.
    Type: Grant
    Filed: April 5, 2002
    Date of Patent: March 9, 2004
    Assignee: Rohm Co., Ltd.
    Inventors: Takahiko Konishi, Masahiko Takeno
  • Publication number: 20030189240
    Abstract: An n-type low impurity concentration semiconductor layer is provided, by epitaxial growth or the like, on a p-type semiconductor substrate. In order to vertically form a semiconductor device in the low impurity concentration semiconductor layer, at least a p-type diffusion region is provided. In a surface of the semiconductor layer, a collector electrode and a base electrode are respectively formed in electrical connection to the n-type low impurity concentration semiconductor layer and the p-type diffusion region. The collector electrode is formed on a surface of the n+-type low resistance region of a polycrystal semiconductor formed depthwise in the low impurity concentration semiconductor layer.
    Type: Application
    Filed: April 5, 2002
    Publication date: October 9, 2003
    Inventors: Takahiko Konishi, Masahiko Takeno
  • Patent number: 6476495
    Abstract: A semiconductor chip 10 is provided to form a large number of cells constituting transistor units arranged on a planar and rectangular semiconductor substrate. On the front surface of the semiconductor chip 10, an emitter electrode 1 to be connected to an emitter and a base electrode 2 to be connected to an base are formed and electrode pads 1a and 2a of the emitter electrode 1 and the base electrode 2 are formed on opposite long sides of the rectangular substrate. On the rear surface of the semiconductor chip 10, a collector electrode 3 to be connected to a collector is formed. The semiconductor chip 10 is bonded to a rectangular island 6a at the tip of a third lead 6. A first lead 4 and a second lead 5 are directly connected to the emitter electrode pad 1a and base electrode pad 2a, respectively.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: November 5, 2002
    Assignee: Rohm Co., Ltd.
    Inventor: Takahiko Konishi
  • Publication number: 20020084511
    Abstract: A semiconductor chip 10 is provided to form a large number of cells constituting transistor units arranged on a planar and rectangular semiconductor substrate. On the front surface of the semiconductor chip 10, an emitter electrode 1 to be connected to an emitter and a base electrode 2 to be connected to an base are formed and electrode pads 1a and 2a of the emitter electrode 1 and the base electrode 2 are formed on opposite long sides of the rectangular substrate. On the rear surface of the semiconductor chip 10, a collector electrode 3 to be connected to a collector is formed. The semiconductor chip 10 is bonded to a rectangular island 6a at the tip of a third lead 6. A first lead 4 and a second lead 5 are directly connected to the emitter electrode pad 1a and base electrode pad 2a, respectively.
    Type: Application
    Filed: December 27, 2001
    Publication date: July 4, 2002
    Applicant: Rohm Co., Ltd
    Inventor: Takahiko Konishi