Patents by Inventor Takahiko Kozaki

Takahiko Kozaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7502380
    Abstract: A packet handler includes an interface circuit corresponding in one-to-one relation to each input/output port of a switch. A switch interface including a disconnection circuit and a distribution circuit controls the packet from each interface circuit to a corresponding input port and the packet from the output ports of the switch to each interface circuit. In a set of interface circuits, one redundant transmission path can be replaced arbitrarily with two non-redundant independent transmission paths. The packet communication system can thus accommodate redundant transmission paths and non-redundant transmission paths in an arbitrary ratio.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: March 10, 2009
    Assignee: Hitachi, Ltd.
    Inventors: Ken'ichi Sakamoto, Yasunari Shinohara, Takahiko Kozaki
  • Patent number: 7095726
    Abstract: An ATM switching system includes PVC allocation circuits 13-i corresponding to output queues 14-i is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has a room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are “input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: August 22, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Kozaki, Morihito Miyagi, Manabu Okamoto
  • Patent number: 7023849
    Abstract: In a packet switching apparatus capable of multicast, the length of a bitmap added to a multicast packet is made variable, depending on the number of line interface cards housed in the packet switching apparatus.
    Type: Grant
    Filed: August 7, 2001
    Date of Patent: April 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Moriwaki, Takahiko Kozaki, Masami Takahashi
  • Patent number: 7023799
    Abstract: A traffic shaper comprises a bandwidth controller 40 having a plurality of leaky bucket units 41-1 to 41-n prepared in correspondence with buffer memories 20-1 to 20-n, and an output queue designation unit 43 for specifying a buffer memory from which a packet is to be read out. Each of the leaky bucket units 41 has a level counter 416 for decrementing the count value at a predetermined rate, and a level increaser 411 to 417 for increasing the count value of the level counter by a value proportional to the product of the length of a transmitted packet and a unitary increment value which is variable depend on the current count value of the level counter.
    Type: Grant
    Filed: February 22, 2002
    Date of Patent: April 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Masayuki Takase, Norihiko Moriwaki, Mitsuhiro Wada, Hiroaki Kasahara, Takahiko Kozaki
  • Patent number: 6977941
    Abstract: A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: December 20, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Masami Takahashi, Akio Makimoto, Takahiko Kozaki, Takayuki Kanno, Yasuo Oginuma, Kaori Nakayama, Mitsuhiro Wada, Norihiko Moriwaki, Masumi Fukano, Yusho Futami
  • Patent number: 6907001
    Abstract: A packet switch which includes input line interfaces for converting variable length packets received from input lines to fixed length cells, a switch unit for switching said packets in cell units, output line interfaces for converting output cells from the switching unit to variable length packets and transmitting the variable length packets over output lines. Each of the input line interfaces has a cell output controller for queuing the fixed length cells for each output line according to the degree of priority of the cells, and for selectively outputting the stored cells in the queues in order of priority, thereby to suppress the transmission of cells with a low priority during the times of congestion.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: June 14, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Kaori Nakayama, Mitsuhiro Wada, Takayuki Kanno, Nobuyuki Yamamoto, Makoto Matsuoka, Yusho Futami, Takahiko Kozaki
  • Publication number: 20050100044
    Abstract: A packet handler includes an interface circuit corresponding in one-to-one relation to each input/output port of a switch. A switch interface including a disconnection circuit and a distribution circuit controls the packet from each interface circuit to a corresponding input port and the packet from the output ports of the switch to each interface circuit. In a set of interface circuits, one redundant transmission path can be replaced arbitrarily with two non-redundant independent transmission paths. The packet communication system can thus accommodate redundant transmission paths and non-redundant transmission paths in an arbitrary ratio.
    Type: Application
    Filed: December 8, 2004
    Publication date: May 12, 2005
    Inventors: Ken' ichi Sakamoto, Yasunari Shinohara, Takahiko Kozaki
  • Patent number: 6850485
    Abstract: A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a pet of interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independent transmission paths. The ATM communication system can thus accommodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
    Type: Grant
    Filed: September 19, 2001
    Date of Patent: February 1, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Ken'ichi Sakamoto, Yasunari Shinohara, Takahiko Kozaki
  • Publication number: 20030206525
    Abstract: The cell output control apparatus includes a cell time slot allotment circuit for allotting, cells to be transmitted, to cell time slots with the cell transmission intervals changed, a first holder circuit for holding the value of ACR (Allowed Cell Rate), a first calculator circuit for calculating the ratio, LCR (Line Cell Rate)/ACR, a quantizer circuit for quantizing the ratio, LCR/ACR and controlling the allotment of cell time slots on the basis of the quantization error produced by the-quantization, a counter for counting the values of cell time slots, a second calculator circuit for calculating the cell time slots for cells, and a second holder circuit for holding the calculated results, whereby it is possible to absorb the quantization error produced when the ratio, LCR/ACR is quantized into an integral value.
    Type: Application
    Filed: September 5, 2001
    Publication date: November 6, 2003
    Inventors: Kota Miyoshi, Takahiko Kozaki, Hajime Abe, Akihiko Takase
  • Patent number: 6611527
    Abstract: A plurality of address chains are assigned to each of such flows as output lines, priority control, etc. in the address management carried out in a switch with a shared buffer. Each of the address chains has a write address register 20 and a read address register 30. The switch is also provided with a distributive pointer 22 for distributing cells in a flow to a plurality of address chains and a write address register selector 21, as well as a read pointer 32 for reading packets from a plurality of the address chains and a read address register selector 31 so as to read the packets through a pipeline with use of those plural address chains.
    Type: Grant
    Filed: February 3, 2000
    Date of Patent: August 26, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Moriwaki, Mitsuhiro Wada, Takahiko Kozaki, Hiroaki Kasahara
  • Publication number: 20030123390
    Abstract: A traffic shaper comprises a bandwidth controller 40 having a plurality of leaky bucket units 41-1 to 41-n prepared in correspondence with buffer memories 20-1 to 20-n, and an output queue designation unit 43 for specifying a buffer memory from which a packet is to be read out. Each of the leaky bucket units 41 has a level counter 416 for decrementing the count value at a predetermined rate, and a level increaser 411 to 417 for increasing the count value of the level counter by a value proportional to the product of the length of a transmitted packet and a unitary increment value which is variable depend on the current count value of the level counter.
    Type: Application
    Filed: February 22, 2002
    Publication date: July 3, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Masayuki Takase, Norihiko Moriwaki, Mitsuhiro Wada, Hiroaki Kasahara, Takahiko Kozaki
  • Patent number: 6507584
    Abstract: An ATM switch that can be expanded to form a large scale ATM switch with minimal hardware additions. The ATM switch includes a plurality of ATM switch units arranged in parallel, a plurality of cell distributors arranged on the input side of the ATM switch units, and a plurality of cell assemblers arranged on the output side of the ATM switch units. Each of the cell distributors distributes ATM cells received from a plurality of incoming highways to a buffer memory having a plurality of queues corresponding to the output ports of the ATM switch units, namely destinations of the ATM cells, and stores the ATM cells to the queues in the buffer memory. Each cell distributor reads ATM cells having the same destination information, and outputs such ATM cells to respective ones of the ATM switch units in parallel. Each of the ATM switch units independently exchanges the received ATM cell in parallel with the other ATM switch units.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: January 14, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Norihiko Moriwaki, Takahiko Kozaki, Takaaki Toyama, Mitsuhiro Wada, Yozo Oguri
  • Publication number: 20030002506
    Abstract: In a packet switching apparatus capable of multicast, the length of a bitmap added to a multicast packet is made variable, depending on the number of line interface cards housed in the packet switching apparatus.
    Type: Application
    Filed: August 7, 2001
    Publication date: January 2, 2003
    Applicant: Hitachi, Ltd.
    Inventors: Norihiko Moriwaki, Takahiko Kozaki, Masami Takahashi
  • Patent number: 6463057
    Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: October 8, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Kozaki, Junichirou Yanagi, Kiyoshi Aiki, Yutaka Ito, Kaoru Aoki, Shinobu Gohara
  • Patent number: 6396831
    Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.
    Type: Grant
    Filed: November 20, 2000
    Date of Patent: May 28, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Kozaki, Junichirou Yanagi, Kiyoshi Aiki, Yutaka Ito, Kaoru Aoki, Shinobu Gohara
  • Patent number: 6389026
    Abstract: An ATM switching system which includes PVC allocation circuits corresponding to output queues. At the time of arrival of the leading cell of each burst data, if the output line has room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells, having the same PVC identification information as the stored identification information are input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
    Type: Grant
    Filed: February 27, 1998
    Date of Patent: May 14, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Kozaki, Morihito Miyagi, Manabu Okamoto
  • Publication number: 20020054602
    Abstract: A packet switch having a structure of writing a variable length packet received from each of input lines into a shared buffer memory on a fixed length data block unit basis, wherein a buffer controller forms an input queue for each input line and, when the last data block of a variable length packet is registered in the input queue, links a linked address list for the input queue to one or a plurality of output queues corresponding to one or a plurality of packet destination output lines.
    Type: Application
    Filed: February 26, 2001
    Publication date: May 9, 2002
    Inventors: Masami Takahashi, Akio Makimoto, Takahiko Kozaki, Takayuki Kanno, Yasuo Oginuma, Kaori Nakayama, Mitsuhiro Wada, Norihiko Moriwaki, Masumi Fukano, Yusho Futami
  • Publication number: 20020012317
    Abstract: A packet handler includes an interface circuit of an ATM handler corresponding in one-to-one relation to each input/output port of an ATM switch. A switch interface including a disconnection circuit and a distribution circuit controls the cell flow from each interface circuit to a corresponding input port and the cell from the output ports of the ATM switch to each interface circuit. In a pet of interface circuits, one redundant transmission path can be replaced arbitrarily with two nonredundant independent transmission paths. The ATM communication system can thus accommodate redundant transmission paths and nonredundant transmission paths in an arbitrary ratio.
    Type: Application
    Filed: September 19, 2001
    Publication date: January 31, 2002
    Inventors: Ken?apos;ichi Sakamoto, Yasunari Shinohara, Takahiko Kozaki
  • Publication number: 20020006129
    Abstract: An ATM switching system includes PVC allocation circuits 13-i corresponding to output queues 14-i is disclosed. At the time of arrival of the leading cell of each burst data, if the output line has a room, the PVC of the burst data is stored as information for admission and identification. The subsequently-arriving cells having the same PVC identification information as the stored identification information are “input to an output buffer, and the cells of the remaining burst data are all discarded. Even when a plurality of burst data compete for the same output line, the fact that all the cells other than the first-arriving admitted burst data are discarded prevents the cells from being input other than within a predetermined bandwidth and localizes the burst data affected by the cell discarding due to output queue overflow.
    Type: Application
    Filed: September 25, 2001
    Publication date: January 17, 2002
    Inventors: Takahiko Kozaki, Morihito Miyagi, Manabu Okamoto
  • Patent number: 6339596
    Abstract: An ATM switching system comprises a switch unit including a plurality of input ports and a plurality of output ports having the same cell transmission rate, and a multiplexer for multiplexing cell trains outputted from at least two output ports into a single cell train and outputting the cell train to a high-speed output line (and/or a demultiplexer for demultiplexing a cell train from an output port into a plurality of cell trains and outputting the cell trains to a plurality of low-speed output lines). The switch unit includes a buffer memory for temporarily storing cells inputted from the input ports while forming a queue chain for each output line to which each cell is to be outputted, a demultiplexer for distributing the cells read from the buffer memory among the output ports in circulation, and a buffer memory control circuit for controlling the write and read operation of cells with the shared buffer memory.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: January 15, 2002
    Assignee: Hitachi, Ltd.
    Inventors: Takahiko Kozaki, Junichirou Yanagi, Kiyoshi Aiki, Yutaka Ito, Kaoru Aoki, Shinobu Gohara