Patents by Inventor Takahiko Sugahara

Takahiko Sugahara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8214725
    Abstract: The Error Correction Code (ECC) circuit generates the first syndrome of write data, which have not been written to the memory. The Error Detection Code (EDC) circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.
    Type: Grant
    Filed: July 9, 2008
    Date of Patent: July 3, 2012
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Publication number: 20120023338
    Abstract: A technique for improving data security is provided. To be specific, in a memory system including an information processing apparatus and a semiconductor memory device, the semiconductor memory device has an interface section that transmits, to the information processing apparatus, data read out from a memory core according to a plurality of communication protocols having different signal transmission/reception methods. Based on a switch command inputted from the information processing apparatus, a communication protocol selection section inputs, to the interface section, a selection signal for selecting a particular communication protocol from the plurality of communication protocols.
    Type: Application
    Filed: April 5, 2010
    Publication date: January 26, 2012
    Applicant: MegaChips Corporation
    Inventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
  • Publication number: 20120008772
    Abstract: A technique allowing an improvement in the confidentiality of information stored in a memory device. A memory controller includes a key generation part that newly generates key information for use in encryption and decryption of information at every predetermined timing, and a data conversion circuit that encrypts information to be outputted to a memory device based on the information and decrypts encrypted information inputted from the memory device based on the key information. In the data conversion circuit, each time the key generation part generates new key information, key information is updated so as to set the new key information as the key information.
    Type: Application
    Filed: April 5, 2010
    Publication date: January 12, 2012
    Applicant: MEGACHIPS CORPORATION
    Inventors: Takahiko Sugahara, Tetsuo Furuichi, Ikuo Yamaguchi, Takashi Oshikiri
  • Patent number: 7877668
    Abstract: When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.
    Type: Grant
    Filed: May 5, 2008
    Date of Patent: January 25, 2011
    Assignee: MegaChips Corporation
    Inventor: Takahiko Sugahara
  • Publication number: 20090044076
    Abstract: The ECC circuit generates the first syndrome of write data, which have not been written to the memory. The EDC circuit generates the second syndrome of verification read data, which have been written to the memory. The EDC circuit detects errors due only to the “read disturb phenomenon” using the second syndrome, the errors occurring in data scanned from the memory. The ECC circuit detects and corrects errors due to the “program disturb phenomenon” and the “read disturb phenomenon” using the first syndrome, the errors occurring in the data in which the errors due only to the “read disturb phenomenon” have been detected. As a result, both the circuit size and the processing time can be reduced.
    Type: Application
    Filed: July 9, 2008
    Publication date: February 12, 2009
    Applicant: MegaChips Corporation
    Inventor: Takahiko SUGAHARA
  • Publication number: 20080294949
    Abstract: When a host system outputs a read command to a memory controller, it measures a load count of a memory area on which a read access load is imposed. Then, when the host system judges that the load count of a memory area reaches a predetermined count, it causes the memory controller to perform an error detection on the memory area. Further, when the host system finds that an error occurs in the memory area, it causes the memory controller to perform an error correction on the memory area. This can avoid or reduce unintended rewriting due to repeated readouts.
    Type: Application
    Filed: May 5, 2008
    Publication date: November 27, 2008
    Applicant: MegaChips Corporation
    Inventor: Takahiko SUGAHARA
  • Publication number: 20080183982
    Abstract: An address comparator stores an address of data read out by a host system. Also, a buffer reads out the data from a memory and stores the data. If an address of data which is expected to be newly read out by the host system is included in addresses which have already been stored in the address comparator, the host system 1 newly reads out the data from the buffer, not from the memory. As a result, it is possible to eliminate or lessen the possibility of unintentional rewriting of data which is likely to be caused due to repeated readout of data.
    Type: Application
    Filed: January 2, 2008
    Publication date: July 31, 2008
    Applicant: MegaChips Corporation
    Inventors: Takahiko SUGAHARA, Tetsuo FURUICHI