Patents by Inventor Takahiko Urai

Takahiko Urai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5892715
    Abstract: In a non-volatile semiconductor memory device, a memory cell array composed of a plurality of non-volatile memory cells is provided. Each word line is connected to a row of the memory cell array, and each bit line is connected to a column of the memory cell array. The memory cell array is divided into N blocks (N is an integer more than 1) in a row direction. A control signal generating section monitors erase operations to each of the N blocks to generate an erase operation history data for each of the N blocks and generates a control signal for each of the N blocks other than a selected block based on the erase operation history data for the corresponding block, when a write operation is performed to the selected block.
    Type: Grant
    Filed: July 7, 1997
    Date of Patent: April 6, 1999
    Assignee: NEC Corporation
    Inventors: Masayoshi Hirata, Takahiko Urai
  • Patent number: 5798547
    Abstract: Flash EEPROM with NAND structure cells has a plurality of memory cell arrays. Each memory cell array has NAND structure of memory cell transistors arranged in column direction and connected serially. Each NAND structure cell has at its ends first and second select transistors, respectively. Control gates of corresponding cell transistors forming the NAND structure cells in respective memory cell arrays are connected together by control gate lines which are formed in row direction constituting word lines. Similarly, control gates of the first and second select transistors of respective memory cell arrays are connected respectively to first and second select gate lines parallel to the word lines.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: August 25, 1998
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5732019
    Abstract: In a method of initializing an electrically erasable non-volatile semiconductor memory device including a memory cell array composed of a plurality of blocks, an erasing operation to each of the memory cell blocks is first executed until a threshold voltage of each memory cell of the each memory block is equal to or lower than a first predetermined value which is lower than a second predetermined value as a final upper limit of a final distribution of threshold voltages of all the memory cells in the each memory block. Next, a programming back operation is executed to the each memory block until each memory cell has the threshold voltage equal to or higher than a third predetermined value as a final lower limit. Finally, a verifying operation is executed to the each memory block to ensure that all the memory cells of the each memory block have the threshold voltages lower than the upper limit.
    Type: Grant
    Filed: May 19, 1997
    Date of Patent: March 24, 1998
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5684747
    Abstract: In a nonvolatile memory device, a write operation is performed upon used memory cells. Then, an erase operation is performed upon the used memory cells as well as unused memory cells. Finally, a write operation is performed upon only the unused memory cells.
    Type: Grant
    Filed: March 11, 1996
    Date of Patent: November 4, 1997
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5484742
    Abstract: A second photo-resist film 6a is formed on first photo-resist film 5a which functions as a mask for etching an oxidation resistant silicon nitride film 3 in a region in which a narrow-channel MOS transistor is to be formed. Ions having p-type are implanted into the surface of a substrate 1 using the first photo-resist film 5a and the second photo-resist film 6a as the masking, to selectively form a p-type ion-implanted layer 7. Then, with heating process, a channel stopper 9a and field oxidation layers 8 are formed, whereby element forming regions partitioned by the field oxidation layers 8 are provided. In this manner, it is possible, at least in the region in which the narrow-channel MOS transistor is to be formed, that the channel stopper is prevented from spreading into the channel region and thereby the reduction of the channel width is prevented.
    Type: Grant
    Filed: October 8, 1992
    Date of Patent: January 16, 1996
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5396499
    Abstract: A semiconductor memory device provided with a first circuit for storing and accessing data and a second circuit for storing and accessing internal information is disclosed, wherein the data and the internal information, when delivered from the first circuit and the second circuit, respectively, are transmitted through a common data line to an output terminal. The feature is that the second circuit is provided with a code generating circuit for generating test codes representing the internal information, and is arranged between the first circuit and the output terminal. The second circuit is operable in two modes, in the first mode transmitting data read from the first circuit directly to the output port through the common data line without any intervention of the code generating circuit, in the second mode delivering the test codes to the common data line.
    Type: Grant
    Filed: September 25, 1992
    Date of Patent: March 7, 1995
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5347486
    Abstract: In an nonvolatile memory device, a transition circuit is provided between an output of a sense amplifier and an input of a write amplifier. In a write/read mode, data is transited from an input/output buffer via the transition circuit to an input of the write amplifier or from an output of the sense amplifier via the transition circuit to an input/output buffer. In a self-refresh mode, data from the output of the sense amplifier is fed back via the transition circuit to the input of the write amplifier.
    Type: Grant
    Filed: November 12, 1993
    Date of Patent: September 13, 1994
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 5018104
    Abstract: A redundant circuit incorporated in a non-volatile memory device has two memory transistors for memorizing a bit of address information one of which is used in a diagnostic operation of component circuits executed before the packaging and the other of which is used for memorizing a bit of address information assigned to a defective memory cell after the packaging, and, for this reason, the other memory transistor is free from the degradation due to the heat attack encountered in the packaging process.
    Type: Grant
    Filed: April 12, 1989
    Date of Patent: May 21, 1991
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 4954729
    Abstract: An output buffer circuit according to the present invention has a complementary inverter circuit and a controlling circuit which produces a pair of driving signals for shifting the complementary inverter circuit between two levels, and the controlling circuit has a pull-down transistor and a pull-up transistor both shifted from the off-states to the on-states on the way between the two levels, so that the driving signals slowly swing their voltage levels in an early stage but steeply reaches the two levels, thereby eliminating any overlapping from the driving signals for elimination of undesirable concurrent on-states from the complementary inverter circuit.
    Type: Grant
    Filed: June 27, 1989
    Date of Patent: September 4, 1990
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 4908798
    Abstract: A semiconductor memory device is provided with a plurality of major memory cell blocks divided into sub-blocks and a redundant memory cell block identical in size with each sub-block. A row decoder circuit as well as two stages of column decoder circuits are provided in association with the major memory cell blocks. Write-in/sense amplifier circuits are located between the two stages of the column decoder circuits and a shifting circuit as well as between the redundant memory cell block and the shifting circuit, so that data bits are amplified after the selection and, then, one of the data bits is replaced with a redundant data bit, if necessary.
    Type: Grant
    Filed: July 20, 1988
    Date of Patent: March 13, 1990
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 4905197
    Abstract: A semiconductor memory having a plurality of programmable memory cells includes discharge circuits for discharging a residual charge which remains on a digital line and a signal line coupling the digit line to a sensing amplifier after a programming of a memory cell is completed. The discharge circuit is coupled to the digit line on the signal line and is activated after the programming is completed. The discharge circuit is inactivated when the programmed data is verified.
    Type: Grant
    Filed: October 21, 1988
    Date of Patent: February 27, 1990
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 4881200
    Abstract: There is disclosed an erasable programmable read only memory device shifted into one of a write-in mode of operation, a read-out mode of operation and a diagnostic mode of operation, the memory device comprises a plurality of input data distributing circuits each provided in association with each memory cell array and operative to simultaneously transfer a data bit to a first write-in circuit for the memory cell array and to a second write-in circuit for a redundant memory cell array in the diagnostic mode of operation, so that the data bit is simultaneously written into both of the memory cell and the redundant memory cell, thereby decreasing the time period consumed in the diagnostic mode of operation.
    Type: Grant
    Filed: October 24, 1988
    Date of Patent: November 14, 1989
    Assignee: NEC Corporation
    Inventor: Takahiko Urai
  • Patent number: 4855956
    Abstract: A semiconductor memory device having a plurality of memory cells of uniform and reliable characteristics is disclosed. The memory device comprises at least one array of memory cells arranged in matrix form of rows and columns and a selection circuit for accessing at least one of the memory cells, and is featured by a plurality of dummy cells arranged along all the peripheries of the array so as to surround the array.
    Type: Grant
    Filed: October 1, 1987
    Date of Patent: August 8, 1989
    Assignee: NEC Corporation
    Inventor: Takahiko Urai