Patents by Inventor Takahiro Irita

Takahiro Irita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070046342
    Abstract: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value or the like to an initial value. A power supply detecting circuit outputs a power supply voltage detection signal indicating that a power supply voltage supplied from the outside enters a predetermined state. A power on reset circuit receives the power supply voltage detection signal, instructs an initial setting operation of the internal circuit at a predetermined timing and, in response to completion of the initial setting operation of the internal circuit, changes an external input/output buffer circuit from a high impedance state to an operable state. Consequently, when the external input/output buffer circuit becomes operable, the initial setting of the internal circuit has already completed.
    Type: Application
    Filed: July 31, 2006
    Publication date: March 1, 2007
    Inventors: Naozumi Morino, Takahiro Irita, Yasuto Igarashi
  • Publication number: 20060291110
    Abstract: A semiconductor integrated circuit device is provided, the circuit being capable of arranging a control signal system, avoiding a danger of failure to check an indefinite signal propagation prevention circuit or the like, further facilitating a check oriented to mounting on an automated tool, and facilitating power shutdown control inside of a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains Area A to Area I. A rule is provided, the rule defining that, in the case where a circuit having a high priority is turned ON, a power domain having its lower priority cannot be turned OFF, thereby facilitating a designing method. In addition, areas capable of applying still another power supply are provided in the independent power areas Area A to Area I. In that area, a relay buffer (repeater) and a clock buffer or an information retaining latch for saving information are integrated.
    Type: Application
    Filed: June 6, 2006
    Publication date: December 28, 2006
    Inventors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Takahiro Irita
  • Patent number: 7124283
    Abstract: The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.
    Type: Grant
    Filed: June 10, 2003
    Date of Patent: October 17, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Keisuke Toyama, Masayuki Kabasawa
  • Publication number: 20050050309
    Abstract: A data processor for executing branch prediction comprises a queuing buffer (23) allocated to an instruction queue and to a return destination instruction queue and having address pointers managed for each instruction stream and a control portion (21) for the queuing buffer. The control portion stores a prediction direction instruction stream and a non-prediction direction instruction stream in the queuing buffer and switches an instruction stream as an execution object from the prediction direction instruction stream to the non-prediction direction instruction stream inside the queuing buffer in response to failure of branch prediction. When buffer areas (Qa1, Qb) are used as the instruction queue, the buffer area (Qa2) is used as a return instruction queue and the buffer area (Qa1) is used as a return instruction queue.
    Type: Application
    Filed: August 27, 2004
    Publication date: March 3, 2005
    Inventors: Hajime Yamashita, Kiwamu Takada, Takahiro Irita, Toru Hiraoka
  • Publication number: 20050027965
    Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when 4corresponding data is detected in a data checking part.
    Type: Application
    Filed: July 6, 2004
    Publication date: February 3, 2005
    Inventors: Tetsuya Yamada, Naohiko Irie, Takahiro Irita, Masayuki Kabasawa
  • Publication number: 20040049658
    Abstract: A method and apparatus are provided for event detection for a multiple instruction-set processor. In one example of the apparatus, a data processing device comprises an instruction execution device configured to execute a first instruction set as specific instructions; an instruction conversion circuit configured to convert instructions of a second instruction set into a first instruction string of the first instruction set, and further configured to supply the first instruction string to the instruction execution device; and a counter device configured to count a prescribed event, wherein the instruction conversion circuit is further configured to output a prescribed instruction when the counter device is satisfied by a prescribed condition.
    Type: Application
    Filed: June 11, 2003
    Publication date: March 11, 2004
    Applicant: Hitachi, Ltd.
    Inventors: Masayuki Kabasawa, Naohiko Irie, Takahiro Irita, Tetsuya Yamada, Takanobu Tsunoda
  • Publication number: 20040031022
    Abstract: Disclosed here is a mechanism provided in an instruction translator for translating an intermediate code (Java bytecode) to an instruction string so as to be interpreted by an instruction execution block corresponding to various upgraded versions of a virtual machine (computer) (VM). Each instruction included in the first instruction group of the intermediate code is translated to an instruction to be interpreted by hardware while each instruction included in the second instruction group is translated by software. The information processing device is configured so that the intermediate code has a storage area for storing information for denoting which of the first and second instruction groups includes the intermediate code. Thus, instruction translation can be made by the same hardware to cope with various upgraded versions of a VM if the values are set in the setting register. In addition, the hardware is not required to be modified to translate instructions even when the VM version is upgraded.
    Type: Application
    Filed: June 30, 2003
    Publication date: February 12, 2004
    Inventors: Masayuki Kabasawa, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Keisuke Toyama, Tetsuya Yamada
  • Publication number: 20040003204
    Abstract: The present invention provides a hardware accelerator, which allows faster switching between processing modes. In an information processing device with a bytecode accelerator BCA for translating a stack-based intermediate code (bytecode) into register-based instructions, a selector SEL for switching between BCA and soft VM is posed between an instruction part FET and a decode part DEC and data transfer paths P4 and P5 are formed between BCA and the register file REG_FILE. When bytecode accelerator BCA is activated, the P3 side is selected by the selector SEL and the translated CPU instructions are transferred to the decode part DEC. If the intermediate language code cannot be translated by the BCA, the processing mode is switched to software processing. During switching between the modes, internal information of BCA can be transferred between BCA and REG_FILE in parallel, achieving faster mode switching.
    Type: Application
    Filed: June 10, 2003
    Publication date: January 1, 2004
    Inventors: Tetsuya Yamada, Naohiko Irie, Takanobu Tsunoda, Takahiro Irita, Keisuke Toyama, Masayuki Kabasawa