Patents by Inventor Takahiro Kumakawa

Takahiro Kumakawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230352247
    Abstract: A capacitor element that has an anode body, a dielectric oxide film layer covering the anode body, and a cathode body formed on the dielectric oxide film layer; an exterior body that covers the capacitor element; a contact layer that is on an anode terminal, which is an end portion of the anode body, and has a surface with a predetermined surface roughness; and an anode-side electrode layer that covers the surface are provided.
    Type: Application
    Filed: July 11, 2023
    Publication date: November 2, 2023
    Inventors: Renki YAMAZAKI, Takahiro KUMAKAWA
  • Patent number: 11742150
    Abstract: A capacitor element that has an anode body, a dielectric oxide film layer covering the anode body, and a cathode body formed on the dielectric oxide film layer; an exterior body that covers the capacitor element; a contact layer that is on an anode terminal, which is an end portion of the anode body, and has a surface with a predetermined surface roughness; and an anode-side electrode layer that covers the surface are provided.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 29, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Renki Yamazaki, Takahiro Kumakawa
  • Patent number: 11715606
    Abstract: A method of manufacturing a solid electrolytic capacitor according to the exemplary embodiment of the present disclosure includes a step of exposing a cathode body end portion, which is a portion of a cathode body, from an exterior body covering the cathode body, which is a conductor, and forming a contact electrode, which is a metal film, on the exposed cathode body end portion.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: August 1, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Kumakawa, Renki Yamazaki
  • Publication number: 20220399168
    Abstract: An electrolytic capacitor including: an element stack including a plurality of capacitor elements; a package body sealing the element stack; and a first and second external electrode. Each of the capacitor elements includes a first end at which the anode body is exposed, and a second end covered with the cathode section, with at least an end surface of the first end exposed from the package body. The capacitor elements include a first capacitor element in which the first end faces a first surface of the package body, and a second capacitor element in which the first end faces a second surface different from the first surface of the package body. The first and second capacitor elements stacked alternately. The first end of the first capacitor element and the first end of the second capacitor element are electrically connected to the first external electrode and the second external electrode, respectively.
    Type: Application
    Filed: October 29, 2020
    Publication date: December 15, 2022
    Inventors: Shinya SUZUKI, Takahiro KUMAKAWA, Junichi KURITA
  • Patent number: 11295902
    Abstract: A solid electrolytic capacitor includes stacked capacitor elements. Each capacitor element includes: an anode body; a dielectric layer provided on a surface of the anode body and including a plurality of voids; a solid electrolyte layer provided on a surface of the dielectric layer; a cathode body provided on a surface of the solid electrolyte layer; and an insulating layer that includes a portion of the dielectric layer and an insulating resin filling the plurality of voids included in the portion of the dielectric layer, the insulating layer insulating and separating between an anode side and a cathode side, and the insulating layer being provided on the anode side of the dielectric layer. An anode portion adhesive resin is provided between adjacent insulating layers.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: April 5, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Renki Yamazaki, Takahiro Kumakawa
  • Patent number: 11227725
    Abstract: A solid electrolytic capacitor having high reliability while maintaining suitable electrical characteristics, and a method for producing the same. The solid electrolytic capacitor includes a plurality of capacitor elements, an exterior body covering the plurality of capacitor elements, a contact layer metallic bonded to an anode terminal portion that is an end portion of the anode body, an anode-side electrode layer provided so as to cover the contact layer, a cathode-side electrode layer electrically connected to the cathode body, an anode-side external electrode provided on the surface of the anode-side electrode layer, and a cathode-side external electrode provided on the surface of the cathode-side electrode layer.
    Type: Grant
    Filed: December 11, 2019
    Date of Patent: January 18, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takahiro Kumakawa, Renki Yamazaki, Shinya Suzuki
  • Publication number: 20210383981
    Abstract: A method of manufacturing a solid electrolytic capacitor according to the exemplary embodiment of the present disclosure includes a step of exposing a cathode body end portion, which is a portion of a cathode body, from an exterior body covering the cathode body, which is a conductor, and forming a contact electrode, which is a metal film, on the exposed cathode body end portion.
    Type: Application
    Filed: May 20, 2021
    Publication date: December 9, 2021
    Inventors: TAKAHIRO KUMAKAWA, RENKI YAMAZAKI
  • Publication number: 20210383982
    Abstract: A capacitor element that has an anode body, a dielectric oxide film layer covering the anode body, and a cathode body formed on the dielectric oxide film layer; an exterior body that covers the capacitor element; a contact layer that is on an anode terminal, which is an end portion of the anode body, and has a surface with a predetermined surface roughness; and an anode-side electrode layer that covers the surface are provided.
    Type: Application
    Filed: May 20, 2021
    Publication date: December 9, 2021
    Inventors: RENKI YAMAZAKI, TAKAHIRO KUMAKAWA
  • Publication number: 20200373269
    Abstract: A joined structure includes: a first member; and a second member that faces the first member and that is joined to the first member via a joining layer. The joining layer includes a metal material and a solder material, apart of the metal material has at least one pore, and the solder material is located in a part of an internal area of the at least one pore. Also disclosed is a joining method that makes it possible to produce the joined structure. Further disclosed is a joining material used in the joining method. The joining method makes it possible to achieve non-pressurization sintering processes while maintaining high precise thickness of a joining layer between the first layer and the second layer based on the spacer.
    Type: Application
    Filed: August 11, 2020
    Publication date: November 26, 2020
    Inventor: Takahiro KUMAKAWA
  • Publication number: 20200335284
    Abstract: A solid electrolytic capacitor having high reliability while maintaining suitable electrical characteristics, and a method for producing the same are provided. The solid electrolytic capacitor includes stacked capacitor elements. The capacitor element includes: an anode body; a dielectric layer provided on a surface of the anode body and including a plurality of voids; a solid electrolyte layer provided on a surface of the dielectric layer; a cathode body provided on a surface of the solid electrolyte layer; and an insulating layer that includes an insulating resin insulating and separating between an anode side and a cathode side, the insulating layer being provided on the anode side of the dielectric layer. The plurality of voids included in the insulating layer are filled with the insulating resin. An anode portion adhesive resin is provided between adjacent insulating layers.
    Type: Application
    Filed: February 20, 2020
    Publication date: October 22, 2020
    Inventors: Renki YAMAZAKI, Takahiro KUMAKAWA
  • Publication number: 20200194187
    Abstract: A solid electrolytic capacitor having high reliability while maintaining suitable electrical characteristics, and a method for producing the same. The solid electrolytic capacitor includes a plurality of capacitor elements, an exterior body covering the plurality of capacitor elements, a contact layer metallic bonded to an anode terminal portion that is an end portion of the anode body, an anode-side electrode layer provided so as to cover the contact layer, a cathode-side electrode layer electrically connected to the cathode body, an anode-side external electrode provided on the surface of the anode-side electrode layer, and a cathode-side external electrode provided on the surface of the cathode-side electrode layer.
    Type: Application
    Filed: December 11, 2019
    Publication date: June 18, 2020
    Inventors: Takahiro KUMAKAWA, Renki YAMAZAKI, Shinya SUZUKI
  • Publication number: 20190172810
    Abstract: A joined structure includes: a first member; and a second member that faces the first member and that is joined to the first member via a joining layer. The joining layer includes a metal material and a solder material, apart of the metal material has at least one pore, and the solder material is located in a part of an internal area of the at least one pore. Also disclosed is a joining method that makes it possible to produce the joined structure. Further disclosed is a joining material used in the joining method. The joining method makes it possible to achieve non-pressurization sintering processes while maintaining high precise thickness of a joining layer between the first layer and the second layer based on the spacer.
    Type: Application
    Filed: November 26, 2018
    Publication date: June 6, 2019
    Inventor: TAKAHIRO KUMAKAWA
  • Patent number: 8299580
    Abstract: A semiconductor wafer includes a plurality of predetermined separation lines extending from an upper surface to a bottom surface; and a semiconductor substrate including a plurality of chip regions segmented by the predetermined separation lines. Tensile stress is applied to regions of the semiconductor substrate provided with the predetermined separation lines.
    Type: Grant
    Filed: February 25, 2010
    Date of Patent: October 30, 2012
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kumakawa, Hideki Kojima, Tomoaki Furukawa
  • Patent number: 7964475
    Abstract: A modified layer 5 and an altered layer 8 are formed outside a dicing point of a dicing area 3. Thus without forming another interface between different physical properties on the dicing point, it is possible to prevent chipping from progressing along a crystal orientation from an interface between a semiconductor element 2 and a semiconductor substrate 1 and from a surface of the semiconductor element during dicing, thereby suppressing the development of chipping to the semiconductor element.
    Type: Grant
    Filed: December 6, 2007
    Date of Patent: June 21, 2011
    Assignee: Panasonic Corporation
    Inventors: Yukiko Haraguchi, Takahiro Kumakawa, Takashi Yui, Kazumi Watase
  • Publication number: 20110108957
    Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).
    Type: Application
    Filed: December 8, 2010
    Publication date: May 12, 2011
    Applicant: Panasonic Corporation
    Inventors: Masaki Utsumi, Takahiro Kumakawa
  • Publication number: 20110039365
    Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.
    Type: Application
    Filed: October 27, 2010
    Publication date: February 17, 2011
    Applicant: PANASONIC CORPORATION
    Inventors: Masaki UTSUMI, Takahiro Kumakawa, Masami Matsuura, Yoshihiro Matsushima
  • Publication number: 20110024882
    Abstract: A semiconductor device includes a semiconductor substrate, a diffusion layer conductive film formed on the semiconductor substrate, an interlayer insulating film layered on the semiconductor substrate, an interconnect pattern and a via pattern formed in the interlayer insulating film, a plurality of circuit regions formed in the semiconductor substrate, and a scribe region formed around the circuit regions and separating the circuit regions from each other. The diffusion layer conductive film is not formed at least in a region to which laser light is emitted in the scribe region.
    Type: Application
    Filed: October 8, 2010
    Publication date: February 3, 2011
    Applicant: PANASONIC CORP
    Inventors: Koji TAKEMURA, Takahiro Kumakawa, Yoshihiro Matsushima
  • Patent number: 7859084
    Abstract: A semiconductor substrate (1) includes a plurality of semiconductor elements (2) in which functional elements are constructed and which is formed in a grid pattern, wherein continuous linear grooves (3) are formed on longitudinal and lateral separating lines (4) that individually separate the plurality of semiconductor elements (2) with the exception of intersections of the separating lines (4) and portions corresponding to corners of each semiconductor element (2).
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: December 28, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaki Utsumi, Takahiro Kumakawa
  • Patent number: 7838323
    Abstract: A method for fabricating a semiconductor device includes: the step (a) of forming a vibrating film on a predetermined region of each of a plurality of chips included in a semiconductor wafer; the step (b) of forming, on the semiconductor wafer, an intermediate film containing a sacrifice layer located on the vibrating film of each of the chips; and the step (c) of forming a fixed film on the intermediate film. This method further includes, after the step (c), the step (d) of subjecting the semiconductor wafer to blade dicing to separate the chips, and the step (e) of removing, by etching, the sacrifice layer to provide a cavity between the vibrating film and the fixed film.
    Type: Grant
    Filed: October 13, 2009
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Masaki Utsumi, Takahiro Kumakawa, Masami Matsuura, Yoshihiro Matsushima
  • Patent number: 7808059
    Abstract: In a semiconductor substrate 1, a plurality of semiconductor elements 2 having diaphragm structures are formed in the form of cells in the longitudinal direction and the lateral direction, and V-grooves 3 are formed by anisotropic etching continuously on only division lines 4 parallel formed in one direction, out of the division lines 4 which are orthogonal to each other and divide the respective semiconductor elements 2 individually.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: October 5, 2010
    Assignee: Panasonic Corporation
    Inventor: Takahiro Kumakawa