Patents by Inventor Takahisa Nitta

Takahisa Nitta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6255731
    Abstract: A semiconductor substrate adapted to giga-scale integration (GSI) comprises a support, at least the surface of which is made of semiconductor, an electroconductive material layer, an insulating layer and a semiconductor layer arranged sequentially in the above order. The electroconductive material layer has at least in part thereof an electroconductive reacted layer obtained by causing two metals, a metal and a semiconductor, a metal and a metal-semiconductor compound, a semiconductor and a metal-semiconductor compound, or two metal-semiconductor compounds to react each other. An electroconductive reaction terminating layer that is made of a material that does not react with the reacted layer is arranged between the reacted layer and the insulating layer or the support.
    Type: Grant
    Filed: July 28, 1998
    Date of Patent: July 3, 2001
    Assignees: Canon Kabushiki Kaisha, Ultraclean Technology Research Institute
    Inventors: Tadahiro Ohmi, Nobuyoshi Tanaka, Takeo Ushiki, Toshikuni Shinohara, Takahisa Nitta
  • Patent number: 6220500
    Abstract: A welding method for materials to be welded which are subjected to fluoride passivation treatment, and a fluoride passivation retreatment method, wherein, when fluoride passivation retreatment is conducted after welding, there is no generation of particles or dust. The method provides superior resistance to fluorine system gases. During fluoride passivation treatment, hydrogen is added to the gas (the back shield gas) flowing through the materials to be welded. In one embodiment of the welding method, the thickness of the fluoride passivated film in a predetermined range from the butt end surfaces of the materials to be welded is set to 10 nm or less, followed by subsequent welding. Furthermore, the fluoride passivation retreatment method, includes the steps of heating at least the welded parts following welding and flowing a gas containing fluorine gas in the interior portion of the parts.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: April 24, 2001
    Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute
    Inventors: Tadahiro Ohmi, Takahisa Nitta, Yasuyuki Shirai, Osamu Nakamura
  • Patent number: 6199092
    Abstract: A semiconductor arithmetic circuit including 2 MOS (Metal Oxide Semiconductor) type transistors, the source electrodes of which are connected to one another and having gate electrodes connected to a signal line having a predetermined potential via switching elements, and having at least two input electrodes capacitively coupled with the gate electrodes, wherein a first voltage and second voltage are applied to, respectively, a first and second input electrode of a first MOS transistor. An input signal voltage is applied to both a first and second input electrode of a second MOS transistor, and then a second switching element is caused to conduct, and the gate electrodes are set to the signal line potential, then the second switching element is isolated and the gate electrodes are placed in an electrically floating state.
    Type: Grant
    Filed: September 22, 1998
    Date of Patent: March 6, 2001
    Assignees: Kabushiki Kaisha UltraClean Technology Research Institute
    Inventors: Tadashi Shibata, Akira Nakada, Masahiro Konnda, Tadahiro Ohmi, Takahisa Nitta
  • Patent number: 6150851
    Abstract: Charge transfer amplifier circuit which is capable of canceling fluctuations in the element characteristics thereof and which conducts highly accurate voltage amplification without the use of a stationary current, and provides a voltage comparator which may be applied to a highly accurate A/D converter which has low power consumption. The charge transfer amplifier circuit is provided with a MOS transistor, a first capacity and a second capacity which are effectively connected to, respectively, the source electrode and the drain electrode of the MOS transistor, a mechanism for setting the region between the terminals of the first capacity and the region between the terminals of the second capacity, respectively, to appropriate predetermined potential differences, and for releasing these, and a mechanism for appropriately externally altering the potential difference between the gate and the source of the MOS transistor. The first capacity is set so as to be larger than the second capacity.
    Type: Grant
    Filed: June 5, 1998
    Date of Patent: November 21, 2000
    Assignees: Tadahiro Ohmi, Kabushiki Kaisha Ultraclean Technology Research Institute
    Inventors: Tadahiro Ohmi, Takahisa Nitta, Koji Kotani
  • Patent number: 6129098
    Abstract: An apparatus for injecting constant quantitative chemicals which is capable of injecting a chemical solution into ultra pure water without generating particulate contamination, and furthermore, the injection interval of the chemical solution to the cleaning nozzle is controlled in units of seconds within a range of a few seconds to 10 or more seconds, and the switching of the type of chemical solution and the changeover to ultra pure water cleaning can be conducted in a short period of time of approximately 1 second.
    Type: Grant
    Filed: August 25, 1998
    Date of Patent: October 10, 2000
    Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, Fujiken, Inc.
    Inventors: Nobuhiro Miki, Takahisa Nitta, Tadahiro Ohmi, Nobukazu Ikeda, Naofumi Yasumoto
  • Patent number: 6039814
    Abstract: A cleaning method comprising the steps of degassing gas dissolved in a cleaning liquid therefrom to a value not more than 5 ppm, loading ultrasonics with a frequency of 1 MHz or more to the cleaning liquid, and cleaning an object for cleaning with the cleaning liquid. Also included, is a cleaning method comprising the steps of: degassing gas dissolved in a surface-active agent-containing cleaning liquid therefrom to a value not more than 5 ppm, loading ultrasonics with a frequency of 1 MHz or more to the cleaning liquid, and cleaning an object for cleaning with the cleaning liquid. Water vapor may be used to sweep gas from a degassing device.
    Type: Grant
    Filed: July 3, 1997
    Date of Patent: March 21, 2000
    Assignees: Tadahiro Ohmi, Kabushiki Kaiha Ultraclean Technology Research Institute
    Inventors: Tadahiro Ohmi, Takahisa Nitta
  • Patent number: 5990060
    Abstract: A cleaning method and a cleaning device which require an extremely short time for processing and also insure and extremely high cleaning effect. Foreign materials deposited on a substrate are removed with a cleaning liquid prepared by mixing a basic and water-soluble fluoride and an oxidizing agent in pure water.
    Type: Grant
    Filed: February 25, 1998
    Date of Patent: November 23, 1999
    Assignee: Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Shunkichi Omae, Takayuki Jizaimaru, Takahisa Nitta
  • Patent number: 5895509
    Abstract: An abrasive composition which can realize chemical-mechanical polishing superior in polishing speed and polishing uniformity.The abrasive composition comprises abrasive grains, isopropyl alcohol, and water. Grain sizes of the abrasive grains are preferably 30 to 250 nm, and the abrasive grains are preferably SiO.sub.2. Further, it is preferable that contents of the abrasive grains and isopropyl alcohol are 5 to 30 wt % and 1 to 15 wt %, respectively. The abrasive composition of the present invention is characterized in that it is deaerated.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: April 20, 1999
    Assignees: Kabushiki Kaisha Ultraclean Technology Research Institute, Tadahiro Ohmi
    Inventors: Tadahiro Ohmi, Takahisa Nitta
  • Patent number: 5858106
    Abstract: A cleaning method for peeling and removing photoresists from a semiconductor by applying ultrasound to a cleaning solution comprising a mixture of an organic solvent diluted with pure water and halogenated alkali metal salts, hydrofluoric acid, or ammonium fluoride. The cleaning method removes organic film such as a photoresist or the like at room temperature, not by dissolving, but rather by peeling. The cleaning liquid does not degrade over a long period of time and, moreover, has a strong cleaning effect yet chemical vapors and water vapors are essentially not generated.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: January 12, 1999
    Assignee: Tadahiro OHMI
    Inventors: Tadahiro Ohmi, Senri Ojima, Takahisa Nitta
  • Patent number: 5105556
    Abstract: Vapor is separated from mist accompanying the vapor by passing the vapor through a porous membrane. The vapor having passed through the membrane is brought into contact with an object to be washed and condenses thereon, whereby the object is washed.
    Type: Grant
    Filed: August 9, 1988
    Date of Patent: April 21, 1992
    Assignee: Hitachi, Ltd.
    Inventors: Hideaki Kurokawa, Katsuya Ebara, Sankichi Takahashi, Harumi Matsuzaki, Hiroaki Yoda, Takahisa Nitta, Isao kouchi, Yukio Hishinuma
  • Patent number: 5060045
    Abstract: Disclosed is a semiconductor integrated circuit device adopting a gate array scheme, having a plurality of layers of wiring formed by a Design Automation system. The device according to the present invention includes a semiconductor substrate having basic cell forming regions, the basic cell forming regions being spaced from each other with wiring channel regions between adjacent basic cell forming regions. The wiring includes at least first-layer wiring lines arranged overlying the wiring channel regions; second-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions; and third-layer wiring lines overlying both the basic cell forming regions and the wiring channel regions. The first-, second- and third-layer wiring lines respectively extend in first, second and third directions, the second direction being different from the first direction.
    Type: Grant
    Filed: October 17, 1989
    Date of Patent: October 22, 1991
    Assignee: Hitachi, Ltd.
    Inventors: Nobuo Owada, Hiroyuki Akimori, Takahisa Nitta, Tohru Kobayashi, Shunji Sasabe, Mikinori Kawaji, Osamu Kasahara
  • Patent number: 4718539
    Abstract: A conveyor means for transporting precision parts is divided into a plurality of block units and compressed air is supplied selectively to each block unit where a transporting pallet is present so as to reduce consumption of compressed air to the minimum. Also, it ensures high carrying efficiency because of its slow starting and slow stopping without reducing the speed during running.
    Type: Grant
    Filed: January 9, 1987
    Date of Patent: January 12, 1988
    Assignees: Hitachi, Ltd., Hitachi Kiden Kogyo, Ltd.
    Inventors: Ichiro Fukuwatari, Seiji Watanabe, Naoyuki Takahashi, Takahisa Nitta, Yoshio Saito
  • Patent number: 4219369
    Abstract: The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.
    Type: Grant
    Filed: August 4, 1978
    Date of Patent: August 26, 1980
    Assignee: Hitachi, Ltd.
    Inventors: Katsumi Ogiue, Takahisa Nitta, Kazumichi Mitsusada, Masato Iwabuchi, Masanori Odaka
  • Patent number: 4111724
    Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.
    Type: Grant
    Filed: December 14, 1976
    Date of Patent: September 5, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Katumi Ogiue, Hiroyuki Kondo, Takashi Ishikawa, Takaaki Mori, Takahisa Nitta
  • Patent number: 4088516
    Abstract: A method of manufacturing a semiconductor device, comprises the steps of masking desired parts of a semiconductor substrate with a material which is impervious to an etchant for the substrate, exposing the substrate to the etchant to thereby etch substrate parts which lie directly beneath end parts of the etchant-impervious material and substrate parts which are not masked, applying a solution preferentially into the parts directly beneath the end parts of the etchant-impervious material among the etched substrate parts, the solution being capable of being converted into a semiconduct or oxide by a predetermined heat treatment, and heat-treating the substrate in order to oxidize the etched substrate surface parts.
    Type: Grant
    Filed: October 29, 1976
    Date of Patent: May 9, 1978
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kondo, Takahisa Nitta, Yoshiro Moriguchi
  • Patent number: RE31506
    Abstract: In the production of a semiconductor integrated circuit device including a selective oxidation step at a high temperature using a nitride film as a mask for isolating respective element regions in a semiconductor wafer with oxidized regions, electrode contact regions and active regions are successively formed in each element region to be surrounded by the oxidized regions and thin oxide films are formed on exposed surfaces of the electrode contact regions, the thin semiconductor oxide films are removed simultaneously by immersed etching, and then electrode metal layers are formed thereon. The thickness of the oxide layer on which the electrode metal layers are formed is maintained almost uniform to ensure the isolation effect. Since a buried region in each element region is required only to make partial contact with the contact region at the bottom portion, the integration density of the elements in the integrated circuit can be increased.
    Type: Grant
    Filed: September 2, 1980
    Date of Patent: January 24, 1984
    Assignee: Hitachi, Ltd.
    Inventors: Katumi Ogiue, Hiroyuki Kondo, Takashi Ishikawa, Takaaki Mori, Takahisa Nitta