Patents by Inventor Takami Hirai

Takami Hirai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9247633
    Abstract: A drive circuit is laminated via a high exothermic element disposed on a power circuit, and it is configured so that the average thermal expansion coefficient of the side of the power circuit of the drive circuit board may be larger than the average thermal expansion coefficient of the side opposite to the power circuit. Thereby, the drive circuit board will be curved in the same direction as the power circuit board when the power circuit board is curved due to heat generation from the high exothermic element accompanying the operation of the module. Thereby, in a high-capacity module, while attaining reduction in size and weight, reduction in surge, and reduction in a loss, poor junction between the high exothermic element of the power circuit and the drive circuit board can be suppressed and heat generating from the high exothermic element can be more effectively released.
    Type: Grant
    Filed: February 19, 2013
    Date of Patent: January 26, 2016
    Assignee: NGK Insulators, Ltd.
    Inventors: Takami Hirai, Shinsuke Yano, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Patent number: 9064758
    Abstract: Problems, such as increase in the electrical resistance in the junction(s) of the terminal(s) of a power semiconductor element and the electrode(s) of a peripheral circuit and decrease in the dielectric strength voltage between adjacent junctions, resulting from the insufficient alignment of the power semiconductor element terminal(s) and the the peripheral circuit electrode(s), in the high-capacity module which is intended to attain reduction in size and weight, reduction in surge, and reduction in loss by lamination of the peripheral circuit onto the power circuit, should be reduced. By preparing level difference(s) in the surface of the peripheral circuit board to more accurately align the peripheral circuit board electrode(s) and the power semiconductor element terminal(s) by contact of the level difference(s) and the lateral face(s) of the power semiconductor element at the time of lamination of the power circuit and the peripheral circuit, the above-mentioned problems can be reduced.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: June 23, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Shinsuke Yano, Takami Hirai, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Patent number: 9012786
    Abstract: A circuit board including a substrate having first and second dielectric layers of first and second dielectrics, the second dielectric containing 8 mass % or more of a glass net former component. At least one portion of an inner layer electrode has approximately two principal surfaces parallel to principal surfaces of the circuit board and a thickness of not less than 50 micrometers in a normal direction of the principal surfaces. The inner layer electrode and second dielectric layer contact with each other, and a ratio t/T of sum total thickness t of the second dielectric layer in contact with the inner layer electrode in a normal direction of the principal surface to sum total thickness T of the first dielectric layer in a normal direction of the principal surface is 0.1 or more.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: April 21, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Shinsuke Yano, Takami Hirai, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Patent number: 8958215
    Abstract: The present invention has an objective to provide a circuit board for a peripheral circuit which can transmit outside heat which generates from a high exothermic element, such as a power semiconductor element, while attaining reduction in size and weight, reduction in surge, and reduction in a loss, in high-capacity modules including power modules, such as an inverter. [Solution Means] In a high-capacity module, by laminating a peripheral circuit using a ceramic circuit board with electrode(s) constituted by thick conductor and embedded therein on a highly exothermic element, overheating of the module is prevented by effective heat dissipation via the circuit board while attaining reduction in size and weight, reduction in surge, and reduction in a loss in the module.
    Type: Grant
    Filed: November 4, 2013
    Date of Patent: February 17, 2015
    Assignee: NGK Insulators, Ltd.
    Inventors: Takami Hirai, Shinsuke Yano, Tsutomu Nanataki, Hirofumi Yamaguchi
  • Patent number: 8912106
    Abstract: The present invention is directed to stably achieve a good thermal conductivity in a glass-ceramic composite material in which aluminum nitride particles are used as filler particles. The glass-ceramic composite material according to the present invention includes a glass matrix and filler particles, each of which is formed by an aluminum nitride particle having a surface layer on which an oxide film is formed, and arranged in the glass matrix. The present invention has characteristic features that the filler particle has a cornerless smooth surface, and that a percentage of the number of filler particles having a sphericity of 0.8 or greater, which is a value of a minor diameter divided by a major diameter, is higher than or equal to 70% on the condition where any fine particle of which particle diameter is smaller than 0.5 ?m is excluded from the number of the filler particles.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: December 16, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Shinsuke Yano, Tsutomu Nanataki, Takami Hirai
  • Patent number: 8878625
    Abstract: The present invention intends to provide a small-sized impedance matching device with a small variation in quality and large-current tolerance. The above described intention of the present invention is achieved by an impedance matching device, which comprises a wiring portion comprising a conductor pattern for wiring, embedded inside or formed on the surface of first dielectric material, and either one or both of an inductor portion comprising a conductor pattern for inductor, embedded inside or formed on the surface of the first dielectric material, or a capacitor portion comprising at least one pair of conductor patterns for capacitor and second dielectric material with a dielectric constant larger than that of the first dielectric material, existing between the pair of conductor patterns for capacitor wherein the thicknesses of the conductor pattern for wiring and the conductor pattern for inductor are 20 ?m or more.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: November 4, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Takami Hirai, Masahiko Namerikawa, Shinsuke Yano
  • Patent number: 8847681
    Abstract: A combiner for a Doherty amplifier includes, on and in a dielectric substrate, a carrier input terminal, a peak input terminal, an output terminal, a combining point for combining an output signal from the carrier amplifier and an output signal from the peak amplifier, a first ?/4 line connected between the carrier input terminal and the combining point, a second ?/4 line connected between the combining point and the output terminal, and a first directional coupler. The first directional coupler includes a third ?/4 line electromagnetically coupled to one, to be monitored, of the first ?/4 line and the second ?/4 line.
    Type: Grant
    Filed: October 21, 2010
    Date of Patent: September 30, 2014
    Assignee: NGK Insulators, Ltd.
    Inventors: Masahiko Namerikawa, Shinsuke Yano, Yasufumi Horio, Tatsuya Tsuruoka, Takami Hirai, Hideaki Okubo, Atsuo Mizuma
  • Publication number: 20140055973
    Abstract: [Summary] [Subject] The present invention has an objective to provide a circuit board for a peripheral circuit which can transmit outside heat which generates from a high exothermic element, such as a power semiconductor element, while attaining reduction in size and weight, reduction in serge, and reduction in a loss, in high-capacity modules including power modules, such as an inverter. [Solution Means] In a high-capacity module, by laminating a peripheral circuit using a ceramic circuit board with electrode(s) constituted by thick conductor and embedded therein on a highly exothermic element, overheating of the module is prevented by effective heat dissipation via the circuit board while attaining reduction in size and weight, reduction in serge, and reduction in a loss in the module.
    Type: Application
    Filed: November 4, 2013
    Publication date: February 27, 2014
    Applicant: NGK Insulators, Ltd.
    Inventors: Takami HIRAI, Shinsuke YANO, Tsutomu NANATAKI, Hirofumi YAMAGUCHI
  • Patent number: 8558640
    Abstract: A directional coupler includes a dielectric substrate having at least an input terminal and an output terminal on a surface thereof, a main line disposed in the dielectric substrate and extending between the input terminal and the output terminal, a first coupling line for monitoring a level of an input signal which is input through the input terminal, the first coupling line being disposed in the dielectric substrate and having an end electrically connected to a first terminating resistor, and a second coupling line for monitoring a level of a reflected signal which is input through the output terminal, the second coupling line being disposed in the dielectric substrate and having an end electrically connected to a second terminating resistor.
    Type: Grant
    Filed: December 15, 2010
    Date of Patent: October 15, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Takami Hirai, Shinsuke Yano, Takanobu Saka
  • Patent number: 8487439
    Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: July 16, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Tani, Takami Hirai, Shinsuke Yano, Tsutomu Nanataki
  • Patent number: 8421215
    Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit board with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: April 16, 2013
    Assignee: NGK Insulators, Ltd.
    Inventors: Makoto Tani, Takami Hirai, Shinsuke Yano, Daishi Tanabe
  • Publication number: 20130049202
    Abstract: In the laminated and sintered ceramic circuit board according to the present invention, at least a portion of the inplane conductor is fine-lined, such that the shape of the cross-section surface of the fine-lined inplane conductor is trapezoid, and the height (a), the length (c) of the lower base and the length (d) of the upper base of the trapezoidal cross-section surfaces, and the interval (b) between the lower bases of the trapezoidal cross-section surfaces of the inplane conductors adjacent in a plane parallel to the principal surfaces of the board meet a certain relation. This provides a laminated ceramic circuit hoard with low open failure rate, short-circuit failure rate and high reliability against high temperature and high humidity in a downsized and short-in-height (thin) semiconductor package.
    Type: Application
    Filed: December 20, 2011
    Publication date: February 28, 2013
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto TANI, Takami Hirai, Shinsuke Yano, Daishi Tanabe
  • Publication number: 20130026636
    Abstract: A circuit board that can decrease thermal stress acting between a semiconductor element and a board in association with temperature alteration and has high mechanical strength (rigidity) as a whole board (including a multilayer wiring layer) is provided. Ceramic base material having a coefficient of thermal expansion close to that of a semiconductor element and inner layer wiring are integrally sintered, and the circuit board is configured so that fine-lined conductor structure corresponding to a multilayer wiring layer in the inner layer wiring has predetermined width, intralayer interval and interlayer interval. Thereby, thermal stress acting between a semiconductor element and the board when the board is exposed to temperature alteration in a condition where it is joined with the semiconductor element is suppressed, rigidity of the board is maintained, and its reliability against temperature cycle is increased.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 31, 2013
    Applicant: NGK Insulators, Ltd.
    Inventors: Makoto TANI, Takami HIRAI, Shinsuke YANO, Tsutomu NANATAKI
  • Publication number: 20120019334
    Abstract: The present invention intends to provide a small-sized impedance matching device with a small variation in quality and large-current tolerance. The above described intention of the present invention is achieved by an impedance matching device, which comprises a wiring portion comprising a conductor pattern for wiring, embedded inside or formed on the surface of first dielectric material, and either one or both of an inductor portion comprising a conductor pattern for inductor, embedded inside or formed on the surface of the first dielectric material, or a capacitor portion comprising at least one pair of conductor patterns for capacitor and second dielectric material with a dielectric constant larger than that of the first dielectric material, existing between the pair of conductor patterns for capacitor wherein the thicknesses of the conductor pattern for wiring and the conductor pattern for inductor are 20 ?m or more.
    Type: Application
    Filed: May 25, 2011
    Publication date: January 26, 2012
    Applicant: NGK Insulators, Ltd.
    Inventors: Takami HIRAI, Masahiko Namerikawa, Shinsuke Yano
  • Publication number: 20110169590
    Abstract: A combiner for a Doherty amplifier includes, on and in a dielectric substrate, a carrier input terminal, a peak input terminal, an output terminal, a combining point for combining an output signal from the carrier amplifier and an output signal from the peak amplifier, a first ?/4 line connected between the carrier input terminal and the combining point, a second ?/4 line connected between the combining point and the output terminal, and a first directional coupler. The first directional coupler includes a third ?/4 line electromagnetically coupled to one, to be monitored, of the first ?/4 line and the second ?/4 line.
    Type: Application
    Filed: October 21, 2010
    Publication date: July 14, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Masahiko Namerikawa, Shinsuke Yano, Yasufumi Horio, Tatsuya Tsuruoka, Takami Hirai, Hideaki Okubo, Atsuo Mizuma
  • Publication number: 20110148544
    Abstract: A directional coupler includes a dielectric substrate having at least an input terminal and an output terminal on a surface thereof, a main line disposed in the dielectric substrate and extending between the input terminal and the output terminal, a first coupling line for monitoring a level of an input signal which is input through the input terminal, the first coupling line being disposed in the dielectric substrate and having an end electrically connected to a first terminating resistor, and a second coupling line for monitoring a level of a reflected signal which is input through the output terminal, the second coupling line being disposed in the dielectric substrate and having an end electrically connected to a second terminating resistor.
    Type: Application
    Filed: December 15, 2010
    Publication date: June 23, 2011
    Applicant: NGK Insulators, Ltd.
    Inventors: Takami HIRAI, Shinsuke YANO, Takanobu SAKA
  • Patent number: 7800465
    Abstract: A passive component is provided with a filter section employing a nonequilibrium input/output system, which has an input side resonator connected to a nonequilibrium input terminal, and an output side resonator coupled with the input side resonator; and a converting section having two double line coupled lines. An output stage of the filter section is connected with an input stage of the converting section through a first capacitor, and an input stage of the filter section is connected with the input stage of the converting section through a second capacitor. Namely, the second capacitor functions as a jump capacitor. The position of an attenuation pole is permitted to be adjusted by a second capacitor in a region low in frequency characteristics.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: September 21, 2010
    Assignee: Soshin Electric Co., Ltd.
    Inventors: Hironobu Kimura, Takami Hirai, Yasuhiko Mizutani, Hirotaka Takeuchi
  • Patent number: 7567152
    Abstract: A dielectric substrate includes a filter unit, a non-balance/balance conversion unit, and a connection unit for electrically connecting the filter unit to the non-balance/balance conversion unit which are formed in the dielectric substrate. A first resonator has an electrode formed on the main surface of a fourth dielectric layer and a via hole penetrating through a first to a third dielectric layers and connecting the electrode to a grounding electrode. A second resonator has an electrode formed on the main surface of the fourth dielectric layer and a via hole penetrating through the first to the third dielectric layers and connecting the electrode to the grounding electrode.
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: July 28, 2009
    Assignee: Soshin Electric Co., Ltd.
    Inventors: Hironobu Kimura, Takami Hirai, Yasuhiko Mizutani, Masaki Urano
  • Publication number: 20090134950
    Abstract: A passive component is provided with a filter section employing a nonequilibrium input/output system, which has an input side resonator connected to a nonequilibrium input terminal, and an output side resonator coupled with the input side resonator; and a converting section having two double line coupled lines. An output stage of the filter section is connected with an input stage of the converting section through a first capacitor, and an input stage of the filter section is connected with the input stage of the converting section through a second capacitor. Namely, the second capacitor functions as a jump capacitor. The position of an attenuation pole is permitted to be adjusted by a second capacitor in a region low in frequency characteristics.
    Type: Application
    Filed: September 28, 2006
    Publication date: May 28, 2009
    Applicant: Soshin Electric Co., Ltd.
    Inventors: Hironobu Kimura, Takami Hirai, Yasuhiko Mizutani, Hirotaka Takeuchi
  • Patent number: 7348868
    Abstract: A passive component comprising one input electrode layer constituting an input terminal, one output electrode layer constituting an output terminal, and four shield electrode layers constituting shield terminals, all formed in the lowermost dielectric layer by via holes. The input electrode layer is connected electrically with an input-side resonance electrode, in the vicinity of the second side face of a dielectric substrate, through a via hole made in the fourth through sixth dielectric layers and an input tap electrode. The output electrode layer is connected electrically with an output-side resonance electrode, in the vicinity of the third side face of the dielectric substrate, through a via hole made in the fourth through sixth dielectric layers and an output tap electrode.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: March 25, 2008
    Assignee: Soshin Electric Co., Ltd.
    Inventors: Masaki Urano, Takami Hirai, Yasuhiko Mizutani, Kouhei Takase