Patents by Inventor Takamitsu Fujimoto
Takamitsu Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10216050Abstract: In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.Type: GrantFiled: January 12, 2016Date of Patent: February 26, 2019Assignee: Japan Display Inc.Inventor: Takamitsu Fujimoto
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Patent number: 9548322Abstract: According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a power source voltage of high level, and a third pad to supply a necessary signal for displaying an image, a common line, a first connection line to connect the first pad with the common line, a second connection line to connect the second pad with the common line, and a third connection line to connect the third pad with the common line, wherein the first connection line and the second connection line are formed of polysilicon in which no impurity is doped, and the third connection line and the common line are formed of polysilicon in which an impurity is doped.Type: GrantFiled: December 4, 2014Date of Patent: January 17, 2017Assignee: Japan Display Inc.Inventors: Takamitsu Fujimoto, Tetsuya Iizuka
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Publication number: 20160124257Abstract: In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.Type: ApplicationFiled: January 12, 2016Publication date: May 5, 2016Applicant: JAPAN DISPLAY INC.Inventor: Takamitsu FUJIMOTO
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Patent number: 9274363Abstract: In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.Type: GrantFiled: February 28, 2013Date of Patent: March 1, 2016Assignee: Japan Display Inc.Inventor: Takamitsu Fujimoto
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Publication number: 20150162352Abstract: According to one embodiment, a wiring substrate includes a pad group of a first pad to supply a power source voltage of low level, a second pad to supply a power source voltage of high level, and a third pad to supply a necessary signal for displaying an image, a common line, a first connection line to connect the first pad with the common line, a second connection line to connect the second pad with the common line, and a third connection line to connect the third pad with the common line, wherein the first connection line and the second connection line are formed of polysilicon in which no impurity is doped, and the third connection line and the common line are formed of polysilicon in which an impurity is doped.Type: ApplicationFiled: December 4, 2014Publication date: June 11, 2015Applicant: Japan Display Inc.Inventors: Takamitsu Fujimoto, Tetsuya Iizuka
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Publication number: 20130258221Abstract: In one embodiment, an array substrate includes an active area in the shape of a rectangle, and first, second third and fourth end portions, surrounding the active area. A source control circuit is electrically connected with one end of the source lines drawn to the third end portion from the active area. First and second common terminals of a common potential are formed in the first end portion. A power supply line is electrically connected with the first common terminal and extends along the second, third and fourth end portions in this order, and connected with the second common terminal. A branch wiring is electrically connected with an intermediate portion of the electric power supply line and the source control circuit, and extending in the first direction.Type: ApplicationFiled: February 28, 2013Publication date: October 3, 2013Inventor: Takamitsu FUJIMOTO
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Patent number: 8411240Abstract: According to one embodiment, a liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, scanning lines, signal lines, pixel switches, first electrodes, a scanning line drive circuit, a second electrode, a voltage supply wiring, a control mechanism, a first switching mechanism, a second switching mechanism, and an output timing switching mechanism. The output timing switching mechanism is configured to simultaneously output a second scanning signal of switching the pixel switch into conductive state to the scanning lines, based on the control signal.Type: GrantFiled: February 17, 2012Date of Patent: April 2, 2013Assignee: Japan Display Central Inc.Inventors: Kenji Harada, Takamitsu Fujimoto, Takahiro Oonuma
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Patent number: 8373831Abstract: According to one embodiment, a liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, scanning lines, signal lines, pixel switches, first electrodes, a scanning line drive circuit, a second electrode, a voltage supply wiring, a control mechanism, a first switching mechanism, a second switching mechanism, and an output timing switching mechanism. The output timing switching mechanism is configured to simultaneously output a second scanning signal of switching the pixel switch into conductive state to the scanning lines, based on the control signal.Type: GrantFiled: February 17, 2012Date of Patent: February 12, 2013Assignee: Japan Display Central Inc.Inventors: Kenji Harada, Takamitsu Fujimoto, Takahiro Oonuma
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Publication number: 20120212472Abstract: According to one embodiment, a liquid crystal display device includes a first substrate, a second substrate, a liquid crystal layer, scanning lines, signal lines, pixel switches, first electrodes, a scanning line drive circuit, a second electrode, a voltage supply wiring, a control mechanism, a first switching mechanism, a second switching mechanism, and an output timing switching mechanism. The output timing switching mechanism is configured to simultaneously output a second scanning signal of switching the pixel switch into conductive state to the scanning lines, based on the control signal.Type: ApplicationFiled: February 17, 2012Publication date: August 23, 2012Inventors: Kenji HARADA, Takamitsu Fujimoto, Takahiro Oonuma
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Patent number: 7973900Abstract: An array substrate of a liquid crystal display device includes an insulating substrate, a gate line extending in a first direction on the insulating substrate, a first insulation film which is disposed to cover the gate line, pixel electrodes which are disposed on the first insulation film in respective pixels, a source line which is disposed on the first insulation film and extends between the pixel electrodes along a second direction, a second insulation film which is disposed to cover the pixel electrode and the source line, and a common electrode which is disposed on the second insulation film in a manner to face the pixel electrode of each of the pixels and to face the gate line, and includes a slit which is opposed to the pixel electrode.Type: GrantFiled: May 6, 2009Date of Patent: July 5, 2011Assignee: Toshiba Matsushita Display Technology Co., Ltd.Inventors: Takamitsu Fujimoto, Shin Morita
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Publication number: 20100007838Abstract: An array substrate of a liquid crystal display device includes an insulating substrate, a gate line extending in a first direction on the insulating substrate, a first insulation film which is disposed to cover the gate line, pixel electrodes which are disposed on the first insulation film in respective pixels, a source line which is disposed on the first insulation film and extends between the pixel electrodes along a second direction, a second insulation film which is disposed to cover the pixel electrode and the source line, and a common electrode which is disposed on the second insulation film in a manner to face the pixel electrode of each of the pixels and to face the gate line, and includes a slit which is opposed to the pixel electrode.Type: ApplicationFiled: May 6, 2009Publication date: January 14, 2010Inventors: Takamitsu Fujimoto, Shin Morita
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Publication number: 20090160748Abstract: A liquid crystal display device, which is configured such that a liquid crystal layer is held between a pair of substrates, includes a scanning line which extends in a row direction of pixels, a signal line which extends in a column direction of the pixels, a pixel electrode which is disposed in association with each of the pixels and includes a slit, a first common electrode which is opposed to the pixel electrode via an interlayer insulation film, and a second common electrode which extends in parallel to the slit and is disposed adjacent to the pixel electrode in the same layer as the pixel electrode.Type: ApplicationFiled: December 15, 2008Publication date: June 25, 2009Inventors: Yohei KIMURA, Takamitsu FUJIMOTO, Junichi KOBAYASHI, Takaharu OGINO
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Patent number: 6303259Abstract: A recording material having a recording layer with microcapsules therein on a support, and a recording method. The microcapsules constituting the recording layer each are composed of a core, a heat-responsive resin layer covering the core, and a shell enveloping the heat-responsive resin layer. The shell is made of a material sensitive to and curable with light having a predetermined wavelength, the core contains a developer (or a dye precursor), and the shell contains a dye precursor (or a developer).Type: GrantFiled: November 24, 1999Date of Patent: October 16, 2001Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuki Kubo, Toshio Kobayashi, Suguru Nagae, Takamitsu Fujimoto, Keiki Yamada
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Patent number: 5888684Abstract: An electrophotographic photosensitive member which comprises an aluminum substrate having an aluminum oxide film at its surface, and, formed sequentially on the substrate, an intermediate layer and a photosensitive layer which contains a photoconductive material, wherein the intermediate layer contains from 5 to 20 wt % of a photoconductive material and has a thickness of from 0.5 to 5 .mu.m, and the resistivity of a laminate of the aluminum oxide film and the intermediate layer is from 10.sup.9 to 3.times.10.sup.10 .OMEGA./3.14 cm.sup.2 when a DC voltage of 20 V is applied.Type: GrantFiled: October 9, 1997Date of Patent: March 30, 1999Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshio Kobayashi, Kazuki Kubo, Kazuko Wakita, Suguru Nagae, Takamitsu Fujimoto
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Patent number: 5783344Abstract: An electrophotographic photosensitive member which comprises an aluminum substrate having an aluminum oxide film at its surface and a photosensitive layer formed on the substrate, which contains a photoconductive material, wherein the aluminum oxide film has a thickness of from 3 to 15 .mu.m, and a resistivity of from 10.sup.9 to 3.times.10.sup.10 .OMEGA./3.14 cm.sup.2 when a DC voltage of 20 V is applied, and an impedance of from 1 to 20 M.OMEGA. at 100 Hz.Type: GrantFiled: October 16, 1997Date of Patent: July 21, 1998Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Toshio Kobayashi, Kazuki Kubo, Suguru Nagae, Takamitsu Fujimoto
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Patent number: 5686216Abstract: An object of the present invention is to provide a photosensitive member having an excellent durability. A sensitizing solution is prepared by adding a polyester resin (resin A) synthesized using an isophthalic acid, neopentyl glycol, phthalic anhydride and adipic acid, other polyester resins, an X-form metal free phthalocyanine as a phthalocyanine type photoconductive compound and a curing agent to a solvent, and is dip-coated on a polyamide layer on an aluminum plate and then dried and cured to give a photosensitive member.Type: GrantFiled: November 14, 1995Date of Patent: November 11, 1997Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuki Kubo, Takamitsu Fujimoto, Suguru Nagae, Toshio Kobayashi, Kazuko Wakita
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Patent number: 5276414Abstract: The improved moistureproof structure for a module circuit is characterized in that a porous film conditioned to have an apparent relative dielectric constant of no more than 2.0 is coated over a stripline a high-frequency circuit, or a high-frequency device formed on a substrate, which porous film may in turn be provided with a resin coating material. The structure insures that the module circuit is moistureproof, thereby protecting it against corrosion to improve its operational reliability without affecting its electrical characteristics.Type: GrantFiled: September 2, 1992Date of Patent: January 4, 1994Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takamitsu Fujimoto, Satoshi Yanaura, Atsuko Noda, Takeji Fujiwara, Hiroyuki Sato, Fumiaki Baba
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Patent number: 5097317Abstract: A resin-sealed semiconductor device includes a semiconductor element mounted on a die frame, bonding wires and external wires connected to the bonding wires. The semiconductor element, the bonding wires and portions of the external leads are coated with porous silica gel impregnated with a sealing resin.Type: GrantFiled: July 13, 1990Date of Patent: March 17, 1992Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takamitsu Fujimoto, Shuichi Kita, Atsuko Noda, Hiroshi Koezuka