Patents by Inventor Takamitsu Ishihara
Takamitsu Ishihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240099010Abstract: A semiconductor memory device includes a gate electrode and a first and second semiconductor layer surrounding the gate electrode. A first electrode layer surrounds the gate electrode and contacts the first semiconductor layer. A second electrode layer surrounds the gate electrode and contacts the first and second semiconductor layers. The first semiconductor layer is between the first and second electrode layers. A third electrode layer surrounds the gate electrode and contacts the second semiconductor layer. The second semiconductor layer is between the second and third electrode layers. A first charge storage layer is between the gate electrode and the first semiconductor layer. A second charge storage layer is between the gate electrode and the second semiconductor layer.Type: ApplicationFiled: August 31, 2023Publication date: March 21, 2024Inventors: Takamitsu ISHIHARA, Kazuya MATSUZAWA
-
Publication number: 20220302160Abstract: According to one embodiment, a semiconductor storage device includes a plurality of electrode films on a substrate alternating with plurality of gaps or insulating layers. A charge storage film is provided on a side surface of each of the plurality of electrode films with a first insulating film placed therebetween. A semiconductor film is provided on a side surface of the charge storage film with a second insulating film placed therebetween. Furthermore, a concentration of a first element in the charge storage film adjacent to each gap or insulating film is higher than a concentration of the first element in the charge storage film adjacent to each electrode film. The first element is one of boron, niobium, or molybdenum.Type: ApplicationFiled: August 24, 2021Publication date: September 22, 2022Inventors: Hiroyuki YAMASHITA, Keiichi SAWA, Yasushi NAKASAKI, Takamitsu ISHIHARA, Junichi KANEYAMA
-
Patent number: 11355694Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains an additive element selected from fluorine (F), sulfur (S), hydrogen (H) and lithium (Li).Type: GrantFiled: September 13, 2019Date of Patent: June 7, 2022Assignee: KIOXIA CORPORATIONInventors: Tadaomi Daibou, Yasushi Nakasaki, Tadashi Kai, Hiroki Kawai, Takamitsu Ishihara, Junichi Ito
-
Patent number: 11316101Abstract: A stack of the embodiment includes: a first magnetic substance; a second magnetic substance; and a first nonmagnetic substance which is disposed between the first magnetic substance and the second magnetic substance and contains at least one first metal element (M1) selected from the group consisting of ruthenium (Ru) and osmium (Os) and at least one second metal element (M2) selected from the group consisting of rhodium (Rh) and iridium (Ir). A magnetic device of the embodiment includes: a third magnetic substance; the stack; and a second nonmagnetic substance which is disposed between the third magnetic substance and the stack.Type: GrantFiled: March 5, 2020Date of Patent: April 26, 2022Assignee: KIOXIA CORPORATIONInventors: Rina Nomoto, Takayuki Tsukagoshi, Yasushi Nakasaki, Masaru Toko, Tadashi Kai, Takamitsu Ishihara
-
Publication number: 20220013579Abstract: According to one embodiment, a magnetic memory device including a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains a first additive element and a second additive element, the first additive element is at least one element selected from sulfur (S), gallium (Ga), aluminum (Al), titanium (Ti), vanadium (V), hydrogen (H), fluorine (F), manganese (Mg), lithium (Li), nitrogen (N) and magnesium (Mg), and the second additive element is lithium (Li).Type: ApplicationFiled: September 23, 2021Publication date: January 13, 2022Applicant: Kioxia CorporationInventors: Tadaomi DAIBOU, Yasushi NAKASAKI, Tadashi KAI, Hiroki KAWAI, Takamitsu ISHIHARA, Junichi ITO
-
Publication number: 20200403150Abstract: A stack of the embodiment includes: a first magnetic substance; a second magnetic substance; and a first nonmagnetic substance which is disposed between the first magnetic substance and the second magnetic substance and contains at least one first metal element (M1) selected from the group consisting of ruthenium (Ru) and osmium (Os) and at least one second metal element (M2) selected from the group consisting of rhodium (Rh) and iridium (Ir). A magnetic device of the embodiment includes: a third magnetic substance; the stack; and a second nonmagnetic substance which is disposed between the third magnetic substance and the stack.Type: ApplicationFiled: March 5, 2020Publication date: December 24, 2020Applicant: KIOXIA CORPORATIONInventors: Rina NOMOTO, Takayuki TSUKAGOSHI, Yasushi NAKASAKI, Masaru TOKO, Tadashi KAI, Takamitsu ISHIHARA
-
Publication number: 20200303628Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including a first magnetic layer having a variable magnetization direction, a second magnetic layer having a fixed magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and containing magnesium (Mg) and oxygen (O). The nonmagnetic layer further contains an additive element selected from fluorine (F), sulfur (S), hydrogen (H) and lithium (Li).Type: ApplicationFiled: September 13, 2019Publication date: September 24, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Tadaomi DAIBOU, Yasushi NAKASAKI, Tadashi KAI, Hiroki KAWAI, Takamitsu ISHIHARA, Junichi ITO
-
Patent number: 10714498Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers.Type: GrantFiled: March 6, 2019Date of Patent: July 14, 2020Assignee: Toshiba Memory CorporationInventors: Harumi Seki, Yuichiro Mitani, Takamitsu Ishihara
-
Patent number: 10707356Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.Type: GrantFiled: March 14, 2019Date of Patent: July 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Megumi Yakabe, Yasushi Nakasaki, Tadaomi Daibou, Tadashi Kai, Junichi Ito, Masahiro Koike, Shogo Itai, Takamitsu Ishihara
-
Publication number: 20200091180Abstract: According to one embodiment, a semiconductor memory device includes: a first interconnect layer; a second interconnect layer adjacent to the first interconnect layer; a semiconductor layer between the first and second interconnect layers; a first charge storage layer between the first interconnect layer and the semiconductor layer; and a second charge storage layer between the second interconnect layer and the semiconductor layer. A first distance between the first and second interconnect layers is shorter than a second distance between the first and second charge storage layers.Type: ApplicationFiled: March 6, 2019Publication date: March 19, 2020Applicant: Toshiba Memory CorporationInventors: Harumi SEKI, Yuichiro MITANI, Takamitsu ISHIHARA
-
Publication number: 20200083289Abstract: According to one embodiment, a magnetic memory device includes a stacked structure including first and second magnetic layers having variable and fixed magnetization directions, respectively, and a nonmagnetic layer provided between the first and second magnetic layers and containing a first compound containing first cationic and anionic elements, and a predetermined-material layer provided around side surfaces of the stacked structure and containing a second compound containing second added cationic and second added anionic elements. An absolute value of a valence number (ionic valency) of the second added cationic element is less than that of the first cationic element, and an absolute value of a valence number (ionic valency) of the second added anionic element is less than that of the first anionic element.Type: ApplicationFiled: March 14, 2019Publication date: March 12, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Megumi YAKABE, Yasushi NAKASAKI, Tadaomi DAIBOU, Tadashi KAI, Junichi ITO, Masahiro KOIKE, Shogo ITAI, Takamitsu ISHIHARA
-
Patent number: 10553729Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: August 29, 2018Date of Patent: February 4, 2020Assignee: Toshiba Memory CorporationInventors: Takamitsu Ishihara, Koichi Muraoka
-
Publication number: 20190027609Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is forced on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: ApplicationFiled: August 29, 2018Publication date: January 24, 2019Applicant: Toshiba Memory CorporationInventors: Takamitsu ISHIHARA, Koichi Muraoka
-
Patent number: 10074749Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: April 11, 2016Date of Patent: September 11, 2018Assignee: TOSHIBA MEMORY CORPORATIONInventors: Takamitsu Ishihara, Koichi Muraoka
-
Patent number: 9830968Abstract: A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.Type: GrantFiled: September 15, 2016Date of Patent: November 28, 2017Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Naoharu Shimomura, Yoshiaki Asao, Takamitsu Ishihara
-
Publication number: 20170270985Abstract: A magnetic memory according to an embodiment includes: at least one memory cell, the memory cell comprising: a conductive layer including a first terminal, a second terminal, and a portion located between the first terminal and the second terminal; a magnetoresistive element including: a first magnetic layer; a second magnetic layer between the portion and the first magnetic layer; and a nonmagnetic layer between the first magnetic layer and the second magnetic layer; a diode including an anode and a cathode, one of the anode and the cathode being electrically connected to the first magnetic layer; and a transistor including third and fourth terminals and a control terminal, the third terminal being electrically connected to the first terminal.Type: ApplicationFiled: September 15, 2016Publication date: September 21, 2017Applicant: Kabushiki Kaisha ToshibaInventors: Naoharu SHIMOMURA, Yoshiaki ASAO, Takamitsu ISHIHARA
-
Patent number: 9691973Abstract: A semiconductor device according to an embodiment includes a first conductive layer, a second conductive layer, and a dielectric film provided between the first and the second conductive layers. The dielectric film including a fluorite-type crystal and a positive ion site includes Hf and/or Zr, and a negative ion site includes O. In the dielectric film, parameters a, b, c, p, x, y, z, u, v and w satisfy a predetermined relation. The axis length of the a-axis, b-axis and c-axis of the original unit cell is a, b, and c, respectively. An axis in a direction with no reversal symmetry is c-axis, a stacking direction of atomic planes of two kinds formed by negative ions disposed at different positions is a-axis, the remainder is b-axis. The parameters x, y, z, u, v and w are values represented using the parameter p.Type: GrantFiled: September 2, 2015Date of Patent: June 27, 2017Assignee: Kabushiki Kaisha ToshibaInventors: Tsunehiro Ino, Riichiro Takaishi, Koichi Kato, Yasushi Nakasaki, Takamitsu Ishihara, Daisuke Matsushita
-
Publication number: 20170160406Abstract: A photodetector according to an embodiment includes; at least one photodiode including: a first electrode; an n-type semiconductor layer disposed on the first electrode; a first p-type semiconductor layer disposed above the n-type semiconductor layer, the first p-type semiconductor layer including a first surface region and a second surface region; a second p-type semiconductor layer disposed in the first surface region of the first p-type semiconductor layer, the second p-type semiconductor layer having a higher p-type impurity concentration than the first p-type semiconductor layer; and a second electrode disposed on the second surface region of the first p-type semiconductor layer and on the second p-type semiconductor layer.Type: ApplicationFiled: February 16, 2017Publication date: June 8, 2017Applicant: KABUSHIKI KAISHA TOSHIBAInventors: KAZUYA MATSUZAWA, SHOGO ITAI, TAKAMITSU ISHIHARA
-
Publication number: 20160225910Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: ApplicationFiled: April 11, 2016Publication date: August 4, 2016Applicant: Kabushiki Kaisha ToshibaInventors: Takamitsu ISHIHARA, Koichi MURAOKA
-
Patent number: 9331167Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.Type: GrantFiled: June 24, 2014Date of Patent: May 3, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Takamitsu Ishihara, Koichi Muraoka