Patents by Inventor Takanori Tsunashima

Takanori Tsunashima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7187421
    Abstract: A liquid crystal display according to one embodiment of the present invention, comprising: signal lines and scanning lines arranged in first and second directions on an insulation substrate; display elements formed in vicinity of cross points of the signal lines and scanning lines; liquid crystal capacitors and auxiliary capacitors which accumulate electric charge in accordance with voltages of the signal lines via said display elements; a signal line drive circuit which drives the signal lines; a scanning line drive circuit which drives the scanning lines; auxiliary capacitor power supply lines arranged in the first direction, to which one ends of said auxiliary capacitors arranged in the second direction are commonly connected; and auxiliary capacitor power supply line voltage control circuits which control voltages of said auxiliary capacitor power supply lines in sync with a cycle which drives said liquid crystal capacitors and said auxiliary capacitors by polarity reverse, wherein said auxiliary capacito
    Type: Grant
    Filed: July 9, 2004
    Date of Patent: March 6, 2007
    Assignee: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Takanori Tsunashima, Hiroyuki Kimura, Masao Karube, Hisao Fujiwara
  • Patent number: 7053876
    Abstract: In a flat panel display device configured to allow moving image data supplied through a signal line 11 to be written to a pixel electrode 13 during typical display operation and further to allow still image data latched in a digital memory 18 to be written to the pixel electrode 13 during still image display operation. When switching from a typical display to a still image display, at least two frames following the completion of the switching operation are assigned as write frames to allow still image data to be written to the digital memory 18. This allows the still image data to be written normally to the digital memory 18 even when the rise times of a memory control signal and a common signal are made longer than a vertical blanking period.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kimura, Takanori Tsunashima
  • Patent number: 7019735
    Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.
    Type: Grant
    Filed: July 16, 2003
    Date of Patent: March 28, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Sasaki, Masaki Miyatake, Hajime Sato, Takanori Tsunashima, Yasuyuki Hanazawa, Hoko Hirai
  • Patent number: 6940483
    Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: September 6, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Maeda, Takanori Tsunashima, Hiroyuki Kimura
  • Publication number: 20050036078
    Abstract: A liquid crystal display according to one embodiment of the present invention, comprising: signal lines and scanning lines arranged in first and second directions on an insulation substrate; display elements formed in vicinity of cross points of the signal lines and scanning lines; liquid crystal capacitors and auxiliary capacitors which accumulate electric charge in accordance with voltages of the signal lines via said display elements; a signal line drive circuit which drives the signal lines; a scanning line drive circuit which drives the scanning lines; auxiliary capacitor power supply lines arranged in the first direction, to which one ends of said auxiliary capacitors arranged in the second direction are commonly connected; and auxiliary capacitor power supply line voltage control circuits which control voltages of said auxiliary capacitor power supply lines in sync with a cycle which drives said liquid crystal capacitors and said auxiliary capacitors by polarity reverse, wherein said auxiliary capacito
    Type: Application
    Filed: July 9, 2004
    Publication date: February 17, 2005
    Applicant: Toshiba Matsushita Display Technology Co., Ltd.
    Inventors: Takanori Tsunashima, Hiroyuki Kimura, Masao Karube, Hisao Fujiwara
  • Patent number: 6778162
    Abstract: Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.
    Type: Grant
    Filed: November 30, 2001
    Date of Patent: August 17, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Kimura, Takashi Maeda, Takanori Tsunashima
  • Patent number: 6771247
    Abstract: A display has display pixels provided with digital memories, respectively. In each display pixel, a pixel electrode and a data line are connected to each other through a first switch, and the pixel electrode and the digital memory are connected to each other through a second switch. In a first display period, the second switches are turned off and the first switches are turned on, to display video data supplied from the data lines. In a second display period, the second switches are turned on and the first switches are turned off, to stop scan and data drivers and display video data stored in the digital memories.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: August 3, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hajime Sato, Hiroyuki Kimura, Takashi Maeda, Takanori Tsunashima
  • Publication number: 20040012584
    Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.
    Type: Application
    Filed: July 16, 2003
    Publication date: January 22, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Sasaki, Masaki Miyatake, Hajime Sato, Takanori Tsunashima, Yasuyuki Hanazawa, Hoko Hirai
  • Publication number: 20040008171
    Abstract: In a flat panel display device configured to allow moving image data supplied through a signal line 11 to be written to a pixel electrode 13 during typical display operation and further to allow still image data latched in a digital memory 18 to be written to the pixel electrode 13 during still image display operation. When switching from a typical display to a still image display, at least two frames following the completion of the switching operation are assigned as write frames to allow still image data to be written to the digital memory 18. This allows the still image data to be written normally to the digital memory 18 even when the rise times of a memory control signal and a common signal are made longer than a vertical blanking period.
    Type: Application
    Filed: June 30, 2003
    Publication date: January 15, 2004
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Kimura, Takanori Tsunashima
  • Patent number: 6639575
    Abstract: There is provided a driving circuit including active matrix type liquid crystal display capable of decreasing the electric power consumption of CMOS buffers contained in a scanning line driving circuit and picture signal line driving circuit. The liquid crystal display has an active matrix type liquid crystal display elements comprising switching elements connected to a plurality of scanning lines and a plurality of picture signal lines perpendicular to the scanning lines. The liquid crystal display includes a digital circuit wherein at least one of a scanning line driving circuit for applying a scanning pulse to the switching elements via the scanning lines and a picture signal line driving circuit for applying a picture signal to the picture signal lines comprises one stage of CMOS buffer or a plurality of CMOS buffers connected in multi stages, the CMOS transistor or each of the CMOS transistors including an N-type thin-film transistor and P-type thin-film transistor which are formed on the same substrate.
    Type: Grant
    Filed: March 17, 2000
    Date of Patent: October 28, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takanori Tsunashima, Yoshiro Aoki, Kazuo Nakamura, Hajime Sato
  • Publication number: 20030174116
    Abstract: During a still picture display period, a normal write voltage is sometimes unable to be applied to a liquid crystal layer 16 because two memory switch elements 21 and 22 are simultaneously turned on, and the output and the inverted output from the digital memory 18 are applied simultaneously to a pixel electrode 13. According to the present invention, the pulse width for the on period of one of the memory switch elements 21 and 22 is narrower than the pulse width for the off period of the other memory switch element, so that the on periods of the two memory switch elements 21 and 22 do not overlap. In this manner, the memory switch elements 21 and 22 are prevented from being turned on at the same time.
    Type: Application
    Filed: December 23, 2002
    Publication date: September 18, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi Maeda, Takanori Tsunashima, Hiroyuki Kimura
  • Patent number: 6617796
    Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 9, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Sasaki, Masaki Miyatake, Hajime Sato, Takanori Tsunashima, Yasuyuki Hanazawa, Hoko Hirai
  • Publication number: 20020075205
    Abstract: Disclosed is a circuit constitution of a display apparatus comprising a digital memory (DM) cell for each pixel. The DM cell is composed of one inverter circuit, and a DM switching circuit for controlling an electrical conduction between a pixel electrode and the DM cell is provided. During a normal displaying period, the DM cell and the pixel electrode are not electrically conducted by the DM switching circuit, and a full-color image displaying is performed by dynamic image data supplied to a signal line. During a still image displaying, the DM cell and the pixel electrode are electrically conducted by the DM switching circuit, and a multi-color image displaying is performed by still image data retained in the DM cell.
    Type: Application
    Filed: November 30, 2001
    Publication date: June 20, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroyuki Kimura, Takashi Maeda, Takanori Tsunashima
  • Publication number: 20020011798
    Abstract: In a flat panel display device in which driving circuits and the like are arranged on an array substrate, a technology to realize a compact size and a low cost of an external control circuit is disclosed. At least one pumping circuit included in the external control circuit is arranged on the array substrate, and an output side capacitor connected between an output portion of the pumping circuit and the ground GND and an input side capacitor of a clock input portion are arranged outside the array substrate.
    Type: Application
    Filed: May 31, 2001
    Publication date: January 31, 2002
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yasushi Sasaki, Masaki Miyatake, Hajime Sato, Takanori Tsunashima, Yasuyuki Hanazawa, Hoko Hirai
  • Publication number: 20010024187
    Abstract: A display has display pixels provided with digital memories, respectively. In each display pixel, a pixel electrode and a data line are connected to each other through a first switch, and the pixel electrode and the digital memory are connected to each other through a second switch. In a first display period, the second switches are turned off and the first switches are turned on, to display video data supplied from the data lines. In a second display period, the second switches are turned on and the first switches are turned off, to stop scan and data drivers and display video data stored in the digital memories.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 27, 2001
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hajime Sato, Hiroyuki Kimura, Takashi Maeda, Takanori Tsunashima