Patents by Inventor Takao KACHI

Takao KACHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10811511
    Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 20, 2020
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Kachi, Yasuhiro Yoshiura
  • Publication number: 20190319109
    Abstract: It is an object of the present invention to easily perform an electric characteristic test for ensuring quality of a semiconductor device on an electrode pattern defect or deficiency. A method of manufacturing a semiconductor device according to the present invention performs, a first etching having a higher selected ratio with respect to a semiconductor material of a first semiconductor layer than a material of a first electrode film over the first electrode film, and removes a region in the first semiconductor layer below a pattern defective part or a deficiency part of the first electrode film at least partially to form an electrode film in the pattern defective part or the deficiency part of the first electrode film.
    Type: Application
    Filed: August 25, 2016
    Publication date: October 17, 2019
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takao KACHI, Yasuhiro YOSHIURA
  • Patent number: 10340133
    Abstract: A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion. Wet etching using hydrofluoric acid is performed, on the silicon substrate on which the silicon oxide film and the structural member are provided. The interface between the silicon oxide film and the structural member is exposed to hydrofluoric acid, in performing the wet etching.
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: July 2, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Kachi, Yasuhiro Yoshiura
  • Publication number: 20180190508
    Abstract: A silicon oxide film having at least one opening portion is formed, on a silicon substrate. A structural member formed of a material less prone to be etched by hydrofluoric acid than a silicon oxide film is formed, wherein the structural member is provided on the silicon oxide film and reaches the silicon substrate in the opening portion. Wet etching using hydrofluoric acid is performed, on the silicon substrate on which the silicon oxide film and the structural member are provided. The interface between the silicon oxide film and the structural member is exposed to hydrofluoric acid, in performing the wet etching.
    Type: Application
    Filed: July 15, 2015
    Publication date: July 5, 2018
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takao KACHI, Yasuhiro YOSHIURA
  • Patent number: 9755037
    Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: September 5, 2017
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Kachi, Masayoshi Tarutani, Yasuhiro Yoshiura
  • Patent number: 9455148
    Abstract: An insulating film (2) is formed on a main surface of a semiconductor substrate (1) that includes an active region and a termination region. The insulating film (2) in the active region is etched to form an opening (3). The insulating film (2) is used as a mask and an impurity is implanted into the semiconductor substrate (1) in a direction tilted by 20° or more from a direction normal to the main surface of the semiconductor substrate (1) while rotating the semiconductor substrate (1) to form a diffusion layer (7) in the active region. The diffusion layer (7) extends wider than the opening (3) up to below the insulating film (2) on the termination region side.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: September 27, 2016
    Assignee: Mitsubishi Electric Corporation
    Inventors: Fumihito Masuoka, Katsumi Nakamura, Takao Kachi
  • Publication number: 20150294871
    Abstract: According to a first aspect of the present invention, a method of manufacturing semiconductor device includes the step of preparing a silicon substrate. The silicon substrate includes an N-type silicon layer on one surface and at least one of a PN junction, an electrode film, and a protective film on another surface. The method includes the steps of forming a Si—Ti junction by forming a first electrode film made of titanium on the N-type silicon layer; forming a second electrode film made of Al—Si on the first electrode film; forming a third electrode film made of Ni on the second electrode film; and heating the silicon substrate after forming the third electrode film. A titanium silicide layer is not formed between the N-type silicon layer and the first electrode film.
    Type: Application
    Filed: December 30, 2014
    Publication date: October 15, 2015
    Applicant: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Takao KACHI, Masayoshi TARUTANI, Yasuhiro YOSHIURA
  • Publication number: 20150255290
    Abstract: An insulating film (2) is formed on a main surface of a semiconductor substrate (1) that includes an active region and a termination region. The insulating film (2) in the active region is etched to form an opening (3). The insulating film (2) is used as a mask and an impurity is implanted into the semiconductor substrate (1) in a direction tilted by 20° or more from a direction normal to the main surface of the semiconductor substrate (1) while rotating the semiconductor substrate (1) to form a diffusion layer (7) in the active region. The diffusion layer (7) extends wider than the opening (3) up to below the insulating film (2) on the termination region side.
    Type: Application
    Filed: December 7, 2012
    Publication date: September 10, 2015
    Applicant: Mitsubishi Electric Corporation
    Inventors: Fumihito Masuoka, Katsumi Nakamura, Takao Kachi
  • Patent number: 8698250
    Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.
    Type: Grant
    Filed: June 18, 2012
    Date of Patent: April 15, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takao Kachi, Yasuhiro Yoshiura, Fumihito Masuoka
  • Publication number: 20130093065
    Abstract: A semiconductor device includes: an N-type drift layer; a P-type anode layer above the N-type drift layer; an N-type cathode layer below the N-type drift layer; a first short lifetime layer between the N-type drift layer and the P-type anode layer; and a second short lifetime layer between the N-type drift layer and the N-type cathode layer. A carrier lifetime in the first and second short lifetime layers is shorter than a carrier lifetime in the N-type drift layer. A carrier lifetime in the N-type cathode layer is longer than the carrier lifetime in the N-type drift layer.
    Type: Application
    Filed: June 18, 2012
    Publication date: April 18, 2013
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takao KACHI, Yasuhiro YOSHIURA, Fumihito MASUOKA