Patents by Inventor Takao Matsumoto

Takao Matsumoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200006394
    Abstract: A thin film transistor according to an embodiment of the present invention includes: a gate electrode supported by a substrate; a gate insulating layer covering the gate electrode; a silicon semiconductor layer being provided on the gate insulating layer and having a crystalline silicon region, the crystalline silicon region including a first region, a second region, and a channel region located between the first region and the second region, such that the channel region, the first region, and the second region overlap the gate electrode via the gate insulating layer; an insulating protection layer disposed on the silicon semiconductor layer so as to cover the channel region and allow the first region and the second region to be exposed; a source electrode electrically connected to the first region; and a drain electrode electrically connected to the second region. The channel region is lower in crystallinity than the first region and the second region.
    Type: Application
    Filed: March 22, 2019
    Publication date: January 2, 2020
    Inventors: YUTA SUGAWARA, MASAKAZU TANAKA, NOBUTAKE NODERA, TAKAO MATSUMOTO
  • Patent number: 10453876
    Abstract: In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape.
    Type: Grant
    Filed: April 20, 2015
    Date of Patent: October 22, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto
  • Publication number: 20190267235
    Abstract: A laser irradiation apparatus includes a light source that generates a laser beam, a projection lens that radiates the laser beam onto a predetermined region of an amorphous silicon thin film deposited on each of a plurality of thin film transistors on a glass substrate, and a projection mask pattern provided on the projection lens and has a plurality of openings so that the laser beam is radiated onto each of the plurality of thin film transistors, wherein the projection lens radiates the laser beam onto the plurality of thin film transistors on the glass substrate, which moves in a predetermined direction, through the projection mask pattern, and the projection mask pattern is provided such that the openings are not continuous in one column orthogonal to the moving direction.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Michinobu Mizumura, Nobutake Nodera, Yoshiaki Matsushima, Masakazu Tanaka, Takao Matsumoto
  • Patent number: 10310347
    Abstract: There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: June 4, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryouhei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20190140102
    Abstract: Provided are a thin film transistor, a display device, and a thin film transistor manufacturing method, in which variation in characteristics is small. The present invention is provided with: a gate electrode formed on a substrate; a gate insulation film formed so as to cover the gate electrode; a semiconductor layer which is formed on the upper side of the gate insulation film and which includes a polysilicon layer disposed, in a plan view, inside a region defined by the gate electrode; an etching stopper layer disposed on the upper side of the polysilicon layer; and a source electrode and a drain electrode provided on the semiconductor layer so as to be separated from each other, wherein the polysilicon layer has first and second regions which are not covered with the etching stopper layer, and a part of the source electrode exists above the first region and a part of the drain electrode exists above the second region.
    Type: Application
    Filed: April 25, 2016
    Publication date: May 9, 2019
    Applicant: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: YOSHIAKI MATSUSHIMA, SHIGERU ISHIDA, RYOHEI TAKAKURA, SATORU UTSUGI, NOBUTAKE NODERA, TAKAO MATSUMOTO, SATOSHI MICHINAKA
  • Patent number: 10263121
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 16, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10256350
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: April 9, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto
  • Patent number: 10243003
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: March 26, 2019
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10038098
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: July 31, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180212065
    Abstract: Provided are a thin film transistor having properties properly adjusted by adjusting crystallinity of a polycrystalline silicon, and a method of manufacturing the same. The silicon layer functioning as a channel layer of a TFT comprises an amorphous part, a first polycrystalline part and a second polycrystalline part. The first and second polycrystalline parts are formed by irradiating the silicon layer with laser beams (energy beams) through the mask comprising the shielding part for shielding the energy beams, the first transmission part for transmitting the energy beams and the second transmission part for transmitting the energy beams at a transmittance lower than that of the first transmission part. By the presence of the second polycrystalline part, properties of the TFT such as an electron mobility are properly adjusted. Further, properties of the TFT can be adjusted easily by adjusting the configuration of the mask.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 26, 2018
    Inventors: Yoshiaki Matsushima, Shigeru Ishida, Ryouhei Takakura, Satoru Utsugi, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20180204957
    Abstract: A method of manufacturing a thin film transistor including: forming a gate electrode on a substrate, forming an insulating film, forming a first silicon layer including an amorphous silicon, irradiating a region of the first silicon layer from a part or the whole of a predetermined region of the first silicon layer to an outside of the predetermined region with an energy beam so as to convert a portion of the first silicon layer into a polycrystalline silicon, a first etching step for etching the first silicon layer while leaving the predetermined region, forming a second silicon layer including an amorphous silicon so as to cover the predetermined region, a second etching step for etching the second silicon layer covering the predetermined region while leaving a part of the second silicon layer, the part larger than the predetermined region, and forming a source electrode and a drain electrode.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Inventors: Satoru Utsugi, Shigeru Ishida, Ryouhei Takakura, Yoshiaki Matsushima, Nobutake Nodera, Takao Matsumoto
  • Publication number: 20180196294
    Abstract: There are provided a display apparatus and a method of manufacturing the display apparatus. The display apparatus includes a pixel having a first thin film transistor and a drive circuit having a second thin film transistor and driving the pixel, wherein a first channel region of the first thin film transistor and a second channel region of the second thin film transistor are configured to have different electrical characteristics (for example, electron mobility, thereby enabling the first thin film transistor and the second thin film transistor to function suitably for the each role thereof).
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryouhei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Patent number: 10008606
    Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 26, 2018
    Assignee: Sakai Display Products Corporation
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180122839
    Abstract: In the present invention, a gate electrode is formed on a substrate surface, and an insulation film is formed on the substrate surface whereon the gate electrode has been formed. A first amorphous silicon layer is formed on the substrate surface whereon the insulation film has been formed. An energy beam is irradiated onto a plurality of required sites spaced from each other in the first amorphous silicon layer to transform each of the required sites into a polysilicon layer. Each of the required sites is situated on the upper side of the gate electrode and serves as a channel region between a source and a drain. This allows other sites, which are in the first amorphous silicon layer and related to the plurality of required sites, to also be irradiated by the energy beam and ablated so as to form at the other sites a cleared portion having a required shape.
    Type: Application
    Filed: April 20, 2015
    Publication date: May 3, 2018
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto
  • Publication number: 20180097120
    Abstract: The thin film transistor includes a gate electrode formed on a surface of a substrate; a first amorphous silicon layer formed on an upper side of the gate electrode; a plurality of polysilicon layers separated by the first amorphous silicon layer and formed on the upper side of the gate electrode with a required spaced dimension; a second amorphous silicon layer and an n+ silicon layer which are formed on the upper side of the plurality of polysilicon layers and the first amorphous silicon layer; and a source electrode and a drain electrode formed on the n+ silicon layer.
    Type: Application
    Filed: March 30, 2015
    Publication date: April 5, 2018
    Inventors: Shigeru Ishida, Nobutake Nodera, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20180017869
    Abstract: The present invention provides a positive type photosensitive siloxane composition in which a film formed by the same has high heat resistance, high strength and high crack resistance, an active matrix substrate in which by-product is not generated, an occurrence of defects is suppressed, and an interlayer insulating film is easily formed at a low cost while having good transmittance, a display apparatus including the active matrix substrate, and a method of manufacturing the active matrix substrate. An active matrix substrate includes a plurality of gate wirings provided so as to extend parallel to each other on an insulating substrate, and a plurality of source wirings provided so as to extend parallel to each other in a direction intersecting the respective gate wirings. An interlayer insulating film and a gate insulating film are interposed at portions including the intersecting portions of the gate wirings and the source wirings, on a lower side of the source wiring.
    Type: Application
    Filed: February 3, 2016
    Publication date: January 18, 2018
    Inventors: Nobutake Nodera, Akihiro Shinozuka, Shinji Koiwa, Masahiro Kato, Takao Matsumoto, Takashi Fuke, Daishi Yokoyama, Katsuto Taniguchi
  • Publication number: 20170162709
    Abstract: The method for manufacturing a thin film transistor includes the processes of forming a gate electrode on a surface of a substrate, forming an insulation film on the surface of the substrate on which the gate electrode is formed, forming a first amorphous silicon layer on the surface of the substrate on which the insulation film is formed, annealing a plurality of required places separated from each other on the first amorphous silicon layer by irradiating the same with an energy beam to change the required places to a polysilicon layer, forming a second amorphous silicon layer by covering the polysilicon layer, forming an n+ silicon layer on a surface of the second amorphous silicon layer, etching the first amorphous silicon layer, the second amorphous silicon layer and the n+ silicon layer.
    Type: Application
    Filed: November 7, 2014
    Publication date: June 8, 2017
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20170154901
    Abstract: The thin film transistor includes: a gate electrode formed on a surface of a substrate; a polysilicon layer formed on an upper side of the gate electrode; an amorphous silicon layer formed on the polysilicon layer so as to cover the same; an n+ silicon layer formed on an upper side of the amorphous silicon layer; and a source electrode and a drain electrode which are formed on the n+ silicon layer, wherein, in a projected state in which the polysilicon layer, the source electrode and the drain electrode are projected onto the surface of the substrate, a part of the polysilicon layer and a part of each of the source electrode and the drain electrode are adapted so as to be overlapped with each other, and in the projected state, a minimum dimension, in a width direction orthogonal to a length direction between the source electrode and the drain electrode, of the polysilicon layer located between the source electrode and the drain electrode is smaller than dimensions in the width direction of the source electrod
    Type: Application
    Filed: March 27, 2015
    Publication date: June 1, 2017
    Applicant: Sakai Display Products Corporation
    Inventors: Nobutake Nodera, Shigeru Ishida, Ryohei Takakura, Yoshiaki Matsushima, Takao Matsumoto, Kazuki Kobayashi, Taimi Oketani
  • Publication number: 20160276374
    Abstract: Provide are: an active matrix substrate with a preferable transmittance in which no by-product is generated because no resist is used and an interlayer insulating film is formed at low cost while the occurrence of a failure is suppressed and a favorable yield is obtained; a display apparatus; and a manufacturing method for the active matrix substrate. A gate electrode and a capacitance wiring are formed on the insulating substrate in the active matrix substrate, and an interlayer insulating film is formed to cover the insulating substrate. On the gate electrode and the capacitance wiring, contact holes Ca and Cb are formed. A gate insulating film is formed on the interlayer insulating film, and a semiconductor film and an n+ film are formed on the portion on the gate insulating film corresponding to the contact hole Ca, each of which is provided with the source electrode and the drain electrode.
    Type: Application
    Filed: October 21, 2014
    Publication date: September 22, 2016
    Inventors: Nobutake NODERA, Akihiro SHINOZUKA, Shinji KOIWA, Masahiro KATO, Takao MATSUMOTO
  • Patent number: 8294854
    Abstract: A liquid crystal display device includes a reflection region for reflecting incident light toward a display surface, wherein, the reflection region includes a metal layer formed on a substrate, a semiconductor layer formed above the metal layer, and a reflective layer formed above the semiconductor layer; and the reflection region includes a first recess formed on a surface of the reflective layer, a second recess formed on the surface of the reflective layer in the first recess, and a third recess formed on the surface of the reflective layer in the second recess. The liquid crystal display device provides a low-cost transflective-type or reflection-type liquid crystal display device having a high image quality.
    Type: Grant
    Filed: April 5, 2007
    Date of Patent: October 23, 2012
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetsuo Kikuchi, Hajime Imai, Hideki Kitagawa, Mitsunori Imade, Yoshihito Hara, Junya Shimada, Takao Matsumoto