Patents by Inventor Takao Moriwaki
Takao Moriwaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11557554Abstract: A semiconductor device includes: a thick copper member in which a semiconductor chip is mounted; a printed circuit board that is disposed on a front surface of the thick copper member and provided with an opening exposing a part of the front surface of the thick copper member, a wiring pattern, and conductive vias connecting the pattern and the thick copper member; a semiconductor chip mounted on the front surface of the thick copper member exposed through the opening and connected to the pattern by a metal wire; an electronic component mounted on a front surface of the printed circuit board opposite to a side facing the thick copper member and connected to the pattern; and a cap or an epoxy resin sealing the front surface of the printed circuit board opposite to a side facing the thick copper member, the chip, the component, and the metal wire.Type: GrantFiled: July 12, 2018Date of Patent: January 17, 2023Assignee: Mitsubishi Electric CorporationInventors: Takao Moriwaki, Katsumi Miyawaki
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Patent number: 11309231Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.Type: GrantFiled: February 21, 2017Date of Patent: April 19, 2022Assignee: Mitsubishi Electric CorporationInventors: Hiroaki Ichinohe, Katsumi Miyawaki, Takao Moriwaki
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Patent number: 11251107Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.Type: GrantFiled: February 21, 2017Date of Patent: February 15, 2022Assignee: Mitsubishi Electric CorporationInventors: Hiroaki Ichinohe, Katsumi Miyawaki, Takao Moriwaki
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Publication number: 20210242144Abstract: A semiconductor device includes: a thick copper member in which a semiconductor chip is mounted; a printed circuit board that is disposed on a front surface of the thick copper member and provided with an opening exposing a part of the front surface of the thick copper member, a wiring pattern, and conductive vias connecting the pattern and the thick copper member; a semiconductor chip mounted on the front surface of the thick copper member exposed through the opening and connected to the pattern by a metal wire; an electronic component mounted on a front surface of the printed circuit board opposite to a side facing the thick copper member and connected to the pattern; and a cap or an epoxy resin sealing the front surface of the printed circuit board opposite to a side facing the thick copper member, the chip, the component, and the metal wire.Type: ApplicationFiled: July 12, 2018Publication date: August 5, 2021Applicant: Mitsubishi Electric CorporationInventors: Takao MORIWAKI, Katsumi MIYAWAKI
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Publication number: 20210175150Abstract: A semiconductor device includes a heat sink, a semiconductor chip and a circuit board that are fixed to the heat sink with a fixing material, plural leads connected to the semiconductor chip and the circuit board via wires, and mold resin provided on the heat sink. The mold resin covers parts of the leads, the wires, and the semiconductor chip, and exposes remainders of the leads. The surfaces of the leads and the heat sink are provided with roughened plating having a surface roughness RMS=150 nm or more. The fixing material is solder or sintered silver. The water absorption rate of the mold resin is 0.24% or less.Type: ApplicationFiled: February 21, 2017Publication date: June 10, 2021Applicant: Mitsubishi Electric CorporationInventors: Hiroaki ICHINOHE, Katsumi MIYAWAKI, Takao MORIWAKI
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Patent number: 8354888Abstract: A power amplifier includes an input matching circuit, an amplifier transistor for amplifying an input signal received through the input matching circuit, an element for varying the collector voltage of the amplifier transistor, a bias circuit for varying the idle current in the amplifier transistor, and a compensation circuit for varying capacitance of the input matching circuit to maintain the phase shift and the input reflection in the power amplifier constant when the collector voltage and the idle current are varied, to prevent a decrease in the efficiency of the power amplifier due to changes in the output power of the amplifier transistor.Type: GrantFiled: August 1, 2011Date of Patent: January 15, 2013Assignee: Mitsubishi Electric CorporationInventors: Takayuki Matsuzuka, Kazuya Yamamoto, Takao Moriwaki
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Publication number: 20120146733Abstract: A power amplifier includes an input matching circuit, an amplifier transistor for amplifying an input signal received through the input matching circuit, an element for varying the collector voltage of the amplifier transistor, a bias circuit for varying the idle current in the amplifier transistor, and a compensation circuit for varying capacitance of the input matching circuit to maintain the phase shift and the input reflection in the power amplifier constant when the collector voltage and the idle current are varied, to prevent a decrease in the efficiency of the power amplifier due to changes in the output power of the amplifier transistor.Type: ApplicationFiled: August 1, 2011Publication date: June 14, 2012Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takayuki Matsuzuka, Kazuya Yamamoto, Takao Moriwaki
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Patent number: 7928804Abstract: A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device.Type: GrantFiled: November 5, 2009Date of Patent: April 19, 2011Assignee: Mitsubishi Electric CorporationInventors: Kazuya Yamamoto, Satoshi Suzuki, Takao Haruna, Takao Moriwaki
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Publication number: 20100301944Abstract: A power amplifier includes: a semiconductor substrate; a preceding-stage amplifying device on the semiconductor substrate, amplifying an input signal; a following-stage amplifying device on the semiconductor substrate, amplifying an output signal of the preceding-stage amplifying device; and an inter-stage matching circuit connecting the preceding-stage amplifying device to the following-stage amplifying device. The preceding-stage amplifying device has a first field effect transistor; the following-stage amplifying device has a heterojunction bipolar transistor; and the inter-stage matching circuit has a capacitance galvanically separating the output terminal of the preceding-stage amplifying device from the input terminal of the following-stage amplifying device.Type: ApplicationFiled: November 5, 2009Publication date: December 2, 2010Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kazuya Yamamoto, Satoshi Suzuki, Takao Haruna, Takao Moriwaki
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Patent number: 7012469Abstract: An integrated circuit device includes a semiconductor amplification element and a bias circuit for applying a bias voltage to the semiconductor amplification element. A power source of the bias circuit is connected to a power source of the semiconductor amplification element via a semiconductor element such that idle current of the semiconductor amplification element is changed in response to a change of a supply voltage of the semiconductor amplification element.Type: GrantFiled: August 29, 2003Date of Patent: March 14, 2006Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Hiroyuki Otsuka
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Patent number: 6946913Abstract: A high-frequency amplifier has an amplifying transistor and a bias circuit that supplies a bias current to the base of the amplifier transistor. The bias circuit has a reference voltage input terminal to which a reference voltage is input from an external source, a first transistor that supplies a bias current to the base of the amplifier transistor in response to the reference voltage, a second transistor whose collector is connected to the connecting point of the first transistor to the base of the amplifying transistor, and whose emitter is grounded, a third transistor that supplies a bias current to the base of the second transistor in response to the reference voltage, and temperature compensation portions connected between the connecting point of the control input terminal to the third transistor and the grounding point.Type: GrantFiled: January 14, 2004Date of Patent: September 20, 2005Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Yuji Yamamoto, Kosei Maemura
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Publication number: 20050174177Abstract: An integrated circuit device includes a semiconductor amplification element and a bias circuit for applying a bias voltage to the semiconductor amplification element. A power source of the bias circuit is connected to a power source of the semiconductor amplification element via a semiconductor element such that idle current of the semiconductor amplification element is changed in response to a change of a supply voltage of the semiconductor amplification element.Type: ApplicationFiled: August 29, 2003Publication date: August 11, 2005Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Hiroyuki Otsuka
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Publication number: 20040251967Abstract: A high-frequency amplifier has an amplifying transistor and a bias circuit that supplies a bias current to the base of the amplifier transistor. The bias circuit has a reference voltage input terminal to which a reference voltage is input from an external source, a first transistor that supplies a bias current to the base of the amplifier transistor in response to the reference voltage, a second transistor whose collector is connected to the connecting point of the first transistor to the base of the amplifying transistor, and whose emitter is grounded, a third transistor that supplies a bias current to the base of the second transistor in response to the reference voltage, and temperature compensation portions connected between the connecting point of the control input terminal to the third transistor and the grounding point.Type: ApplicationFiled: January 14, 2004Publication date: December 16, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Yuji Yamamoto, Kosei Maemura
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Patent number: 6750718Abstract: Base biases that are supplied to an RF transistor when the RF transistor is in high output power operation and in low output power operation, respectively, are supplied from different voltage sources. When an amplifier is in high output power operation, a base bias is output from a bias circuit unit. At this time, the RF transistor operates at a constant voltage based on the bias that is output from the bias circuit unit. When the amplifier is in low output power operation, a base bias is supplied from a reference voltage terminal via a resistor. This makes it possible to decrease variation in base bias voltage. When the amplifier is in low output power operation, operation of the bias circuit unit is prohibited and hence no current is consumed in the bias circuit unit, whereby efficiency of the amplifier is increased.Type: GrantFiled: November 26, 2002Date of Patent: June 15, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Kousei Maemura
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Publication number: 20040004518Abstract: Base biases that are supplied to an RF transistor when the RF transistor is in high output power operation and in low output power operation, respectively, are supplied from different voltage sources. When an amplifier is in high output power operation, a base bias is output from a bias circuit unit. At this time, the RF transistor performs a constant voltage operation based on the bias that is output from the bias circuit unit. When the amplifier is in low output power operation, a base bias is supplied from a reference voltage terminal via a resistor. This makes it possible to decrease a variation in base bias voltage. When the amplifier is in low output power operation, operation of the bias circuit unit is prohibited and hence no current is consumed in the bias circuit unit, whereby an efficiency of the amplifier can be increased.Type: ApplicationFiled: November 26, 2002Publication date: January 8, 2004Applicant: Mitsubishi Denki Kabushiki KaishaInventors: Takao Moriwaki, Kousei Maemura
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Patent number: 6577200Abstract: A high-frequency semiconductor amplifier circuit minimizing deterioration of high-frequency characteristics and attaining high thermal stability. A driver stage of a power amplifier has a multi-stage configuration with multi-finger HBTs connected in shunt with each other, each multi-finger HBT having a single emitter. An output stage has a single stage configuration multi-finger HBTs connected in shunt with each other, each HBT including two emitters. As a result, while an increase in capacitance of a p-n junction between an emitter layer and a base layer of the driver stage is prevented, thermal nonuniformity arising in the output stage is minimized. Thus, a power amplifier as a whole is configured with high thermal stability without deterioration of a high-frequency characteristic of the power amplifier.Type: GrantFiled: March 5, 2001Date of Patent: June 10, 2003Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Takao Moriwaki
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Publication number: 20020024391Abstract: There is provided a high-frequency semiconductor device having an amplifier circuit, which amplifier minimizes deterioration of a high-frequency characteristic and attains high thermal stability. A driver stage of a power amplifier is formed so as to assume a multi-stage configuration by means of connecting multi-finger HBTs in shunt with each other, each multi-finger HBT comprising a single emitter. An output stage is formed so as to assume a single stage configuration by means of connecting multi-finger HBTs in shunt with each other, each HBT comprising two emitters. As a result, while an increase in capacity of p-n junction between an emitter layer and a base layer of the driver stage is prevented, thermal nonuniformity arising in the output stage is minimized. Thus, a power amplifier as a whole is configured with high thermal stability without deterioration of a high-frequency characteristic of the power amplifier.Type: ApplicationFiled: March 5, 2001Publication date: February 28, 2002Inventor: Takao Moriwaki
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Patent number: 6066993Abstract: A duplexer circuit apparatus includes (a) a transmission arm circuit including a first switching circuit which is connected between a transmitter and an antenna, is turned on during transmission, and is turned off during reception, and (b) a reception arm circuit including a second switching circuit which is connected between a receiver and the antenna, is turned off during transmission, and is turned on during reception. In the duplexer circuit apparatus, either the transmitter or the receiver is selectively connected to the antenna, and the transmission arm circuit further includes a cascode amplifier, and an impedance matching inductor connected between the cascode amplifier and the antenna. In this case, the cascode amplifier may be replaced by a source-grounded amplifier constituted by only the FET.Type: GrantFiled: July 10, 1998Date of Patent: May 23, 2000Assignee: Mitsubishi Denki Kabushiki KaishaInventors: Kazuya Yamamoto, Takao Moriwaki