Patents by Inventor Takao Nishimura
Takao Nishimura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8134240Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.Type: GrantFiled: September 11, 2009Date of Patent: March 13, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 8125789Abstract: A wiring substrate includes a plurality of electrode terminals, to which external connection terminals of an electronic component are coupled, arranged in a row on one principal surface thereof, wherein the electrode terminals each include: a first linear portion; a second linear portion extending from an end of the first linear portion in a direction different from a direction of the first linear portion; and a bent portion that is a part where the first linear portion and the second linear portion are connected.Type: GrantFiled: March 12, 2008Date of Patent: February 28, 2012Assignee: Fujitsu Semiconductor LimitedInventor: Takao Nishimura
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Patent number: 8076785Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.Type: GrantFiled: June 26, 2006Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
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Patent number: 8076769Abstract: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.Type: GrantFiled: November 21, 2008Date of Patent: December 13, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshikazu Kumagaya
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Publication number: 20110278723Abstract: A semiconductor device includes a semiconductor element having a main surface where an outside connection terminal pad is provided. The semiconductor element is connected to a conductive layer on a supporting board via a plurality of convex-shaped outside connection terminals provided on the outside connection terminal pad and a connection member; and the connection member commonly covers the convex-shaped outside connection terminals.Type: ApplicationFiled: August 1, 2011Publication date: November 17, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Takao Nishimura, Yoshikazu Kumagaya, Akira Takashima, Kouichi Nakamura, Kazuyuki Aiba
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Patent number: 8048719Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: GrantFiled: April 6, 2009Date of Patent: November 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Tetsuya Hiraoka
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Patent number: 7973404Abstract: A relay board provided in a semiconductor device, including an entire main surface that is made of a conductive material. The relay board may further include a substrate made of the same material as at least one semiconductor element provided in the semiconductor device. The main surface of the relay board may be formed at an upper part of the substrate.Type: GrantFiled: March 17, 2006Date of Patent: July 5, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa, Yoshikazu Kumagaya
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Publication number: 20110092065Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: ApplicationFiled: December 22, 2010Publication date: April 21, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Eiji YOSHIDA, Takao OHNO, Yoshito AKUTAGAWA, Koji SAWAHATA, Masataka MIZUKOSHI, Takao NISHIMURA, Akira TAKASHIMA, Mitsuhisa WATANABE
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Publication number: 20110075785Abstract: An object is to reduce radiation exposure in a nuclear plant. A nuclear plant 1 is a nuclear power generating plant where steam is generated by thermal energy generated by nuclear fission of a nuclear fuel 2C in a nuclear reactor 2, and a turbine 8 is driven by the steam to generate heat by a power generator 10. After a nuclear plant 1 is newly constructed, when a primary cooling system of the nuclear reactor 2 raises the temperature to around a power operation temperature for the first time, zinc is injected into a primary coolant C1 present in the primary cooling system by a zinc injector 20.Type: ApplicationFiled: April 3, 2009Publication date: March 31, 2011Applicant: MITSUBISHI HEAVY INDUSTRIES, LTD.Inventors: Takao Nishimura, Ryuji Umehara
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Patent number: 7906852Abstract: A semiconductor device, includes a wiring board; a first semiconductor element mounted on the wiring board; a second semiconductor element mounted on the first semiconductor element so that a position of the second semiconductor element is shifted relative to a position of the first semiconductor element; wherein a part of a main surface of the second semiconductor element faces the first semiconductor element; and an electrode pad provided on the main surface of the second semiconductor element is connected to a second semiconductor element connection pad of the wiring board by a connection part.Type: GrantFiled: October 5, 2007Date of Patent: March 15, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Yoshiaki Narisawa
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Patent number: 7884459Abstract: A semiconductor device is provided that forms a three-dimensional semiconductor device having semiconductor devices stacked on one another. In this semiconductor device, a hole is formed in a silicon semiconductor substrate that has an integrated circuit unit and an electrode pad formed on a principal surface on the outer side. The hole is formed by etching, with the electrode pad serving as an etching stopper layer. An embedded electrode is formed in the hole. This embedded electrode serves to electrically lead the electrode pad to the principal surface on the bottom side of the silicon semiconductor substrate.Type: GrantFiled: September 15, 2008Date of Patent: February 8, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Eiji Yoshida, Takao Ohno, Yoshito Akutagawa, Koji Sawahata, Masataka Mizukoshi, Takao Nishimura, Akira Takashima, Mitsuhisa Watanabe
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Patent number: 7880276Abstract: A wiring board where an electronic component is mounted on a main surface via a bump and at least a part of the periphery of the electronic component is covered with resin, the wiring board includes a dam provided at least at a part of the periphery of an area where the electronic component is mounted, on the main surface of the wiring board; wherein a surface of the dam contacting the resin has a configuration where a curved line is continuously formed.Type: GrantFiled: January 4, 2008Date of Patent: February 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Kazuyuki Aiba
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Publication number: 20100258926Abstract: A relay board provided in a semiconductor device includes a first terminal, and a plurality of second terminals connecting to the first terminal by a wiring. The wiring connecting to the first terminal is split on the way so that the wiring connects to each of the second terminals.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Applicant: FUJITSU SEMICONDUCTOR LIMITED (Formerly Fujitsu Microelectronics Limited)Inventors: Takao Nishimura, Kouichi Nakamura
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Patent number: 7755203Abstract: A circuit substrate for improving the reliability and productivity of a semiconductor device, and that semiconductor device. In a circuit substrate to which a semiconductor element is to be flip-chip mounted, at least one island-shaped electrically conductive layer is selectively disposed together with a wiring layer at an element mounting area where the semiconductor element is to be mounted, and an insulating resin layer is disposed over the island-shaped electrically conductive layer. The semiconductor element is secured at the element mounting area to the circuit substrate by an adhesion material to make a semiconductor device. With this, delaminating of the wiring layer inside the semiconductor device is suppressed, and the damage of an electrode is suppressed. The circuit substrate has high reliability and the semiconductor device, having the circuit substrate, is implemented.Type: GrantFiled: February 20, 2007Date of Patent: July 13, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Kazuyuki Aiba
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Patent number: 7687319Abstract: The present invention provides a method for manufacturing a semiconductor device which includes at least supplying an adhesive for bonding an electronic component which has a plurality of bumps with a substrate which has a plurality of bonding pads corresponding to the bumps, to at least a portion of the substrate, between the electronic component and the substrate, flow-casting the adhesive on the substrate by a flow-casting unit, in such a manner that the expression S1/S0>1 is satisfied, where S0 is the total contact surface area with the substrate of the adhesive supplied to the substrate, and S1 is the total contact surface area with the substrate of the adhesive after the flow-casting, and curing the adhesive while making the adhesive contact with the electronic component and the substrate in a state where the bumps are abutted against the bonding pads.Type: GrantFiled: April 7, 2008Date of Patent: March 30, 2010Assignee: Fujitsu Microelectronics LimitedInventors: Takao Nishimura, Kouichi Nakamura
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Patent number: 7679188Abstract: To provide a high-performance, highly-reliable semiconductor device in which an adhesive used to mount (e.g., flip-chip mount) a semiconductor chip on a substrate has less air bubbles, and a low-cost, efficient method for manufacturing the same. Semiconductor device 10 of the present invention includes semiconductor chip 11 having a plurality of electrode pads 12, and substrate 14 having a plurality of electrode terminals 15 at positions corresponding to electrode pads 12. A plurality of bumps 13, each composed of base part 13A and protruding part 13B having a diameter smaller than the diameter of base part 13A, is formed on at least one of electrode pads 12 in such a way that the respective base parts 13A of bumps 13 are in contact with each other, and semiconductor chip 11 is bonded to substrate 14 with adhesive 17 in a state where bumps 13 are electrically connected to electrode terminals 15.Type: GrantFiled: July 17, 2006Date of Patent: March 16, 2010Assignee: Fujitsu Microelectronics LimitedInventor: Takao Nishimura
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Publication number: 20090321927Abstract: To provide a small, high-performance semiconductor device in which contact between adjacent wires is prevented for increased flexibility in designing a wiring layout, and an efficient method for manufacturing the semiconductor device. The semiconductor device includes a substrate 10 having an electrode 21A arranged on its surface; and a first semiconductor element 11A which includes an electrode 22 arranged on its surface and which is supported by the substrate 10, wherein a first wire 41 is connected through a first bump 31 to at least one of the electrodes over the substrate 10 and semiconductor element 11A (i.e., at least one of the electrodes 21 and 22), and a second wire 42 is connected through a second bump 32 to a bonding portion of the wire 41.Type: ApplicationFiled: September 11, 2009Publication date: December 31, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takao Nishimura, Yoshiaki Narisawa
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Publication number: 20090309239Abstract: A semiconductor device includes a supporting board, a first semiconductor element mounted on a main surface of the supporting board; and an electronic component provided between the supporting board and the first semiconductor element; wherein the supporting board includes a concave part formed in a direction separated from the first semiconductor element; and at least a part of the electronic component is accommodated in the concave part.Type: ApplicationFiled: February 27, 2009Publication date: December 17, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takao Nishimura, Takayuki Norimatsu
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Publication number: 20090243092Abstract: A semiconductor device includes a semiconductor element; a plate member disposed opposite to an electronic-circuit forming portion of the semiconductor element; and an elastic body arranged in a compressed state between the semiconductor element and the plate member, wherein the elastic body includes at least one first protruding portion at one end in an extension direction of the elastic body, the first protruding portion being formed opposite to the electronic-circuit forming portion of the semiconductor element, and the semiconductor element and the plate member are fastened by an adhesive agent.Type: ApplicationFiled: November 21, 2008Publication date: October 1, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Takao NISHIMURA, Yoshikazu KUMAGAYA
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Publication number: 20090191702Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: FUJITSU LIMITEDInventors: Takao NISHIMURA, Tetsuya Hiraoka