Abstract: Methods and systems are disclosed for controlling fly-height of a read/write (RW) head. In an embodiment, a RW channel detects a servo gate signal and toggles a mode signal within a preamplifier from a RW data mode signal to a fly-height control (FHC) mode signal. In response to the FHC mode signal, the RW channel transmits FHC data over a differential interface to the preamplifier.

Abstract: Methods and systems are disclosed for controlling fly-height of a read/write (RW) head. In an embodiment, a RW channel detects a servo gate signal and toggles a mode signal within a preamplifier from a RW data mode signal to a fly-height control (FHC) mode signal. In response to the FHC mode signal, the RW channel transmits FHC data over a differential interface to the preamplifier.

Abstract: An information reproducing apparatus which reproduces information recorded on a medium includes an asymmetry correction circuit configured to correct an asymmetry of a signal read from a medium. The apparatus also includes a first high pass filter installed before the asymmetry correction circuit and configured to remove noise in the signal by a first cut-off frequency. The apparatus also includes a second high pass filter installed after the asymmetry correction circuit and configured to remove the noise in the signal by a second cut-off frequency, wherein the second cut-off frequency is higher than the first cut-off frequency.

Abstract: A Post-Viterbi processor generates a plurality of candidate codewords based on a plurality of dominant error patterns for a particular communication channel. The Post-Viterbi processor selects one among the candidate codewords as a corrected codeword upon determining that the candidate codeword is error free.

Abstract: A record reproduction apparatus includes an encoding unit that encodes sector data to be written into a recording medium, by dividing the data into a predetermined number of blocks, and an iterative decoding unit that iteratively decodes the sector data read from the recording medium, by dividing the sector data into the predetermined number of blocks.

Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

Abstract: An ECC determining unit determines whether an error detected by using an ECC has been corrected. When the detected error has not been corrected, an equalizer output sequence transfer unit transfers an equalizer output sequence yk stored in an equalizer output sequence storage unit to a transfer data storage unit in a hard disk controller, so that a high-performance decoding unit (software) performs repetitive decoding, using the transferred equalizer output sequence yk.

Abstract: A timing recovery method samples, equalizes and detects a signal reproduced from a recording medium and to output a detection signal, controls sampling positions based on a phase error between the equalized signal and the detection signal, and obtains likelihood information which is related to a bit having a probability of error which exceeds a predetermined value, based on the equalized signal. The control of the sampling positions is suppressed during a time which is based on the likelihood information.

Abstract: In a training operation for optimizing a multiplication coefficient for each tap of an FIR equalizer equalizing a read signal read from a recording medium, as a restricted coefficient updating vector applied for updating the multiplication coefficient for each tap of an FIR filter, a vector is utilized which is obtained by projecting, onto a plane perpendicular to a predetermined restricting conditioning vector, a coefficient updating vector determined based on an equalizer error between the output of the FIR equalizer and a reproduction output determined therefrom and a delayed input value for each tap of the FIR equalizer.

Abstract: A Post-Viterbi processor generates a plurality of candidate codewords based on a plurality of dominant error patterns for a particular communication channel. The Post-Viterbi processor selects one among the candidate codewords as a corrected codeword upon determining that the candidate codeword is error free.

Abstract: A disk writing apparatus includes: a temperature sensor sensing an ambient temperature of a disk; a sync mark generator generating a sync mark having a pattern when a writing temperature indicating an ambient temperature at which data is written on the disk is sensed, wherein the pattern of the sync mark corresponds to the sensed writing temperature; a writing controller outputting the writing temperature sensed by the temperature sensor to the sync mark generator; a multiplexer adding the sync mark generated by the sync mark generator to the data; and a writing unit writing the data to which the sync mark is added on the disk. Accordingly, error rates when data is written and when data is reproduced can be improved by optimally compensating for the disk writing temperature and the disk reproducing temperature using parameters of devices of an hard disk drive.

Abstract: A recording and reproducing apparatus having an ECC-less error correction function, includes an erasure detector generating an erasure flag indicating erasure of a read signal; and an iterative decoder having two soft-in/soft-out (SISO) decoders, i.e., an inner decoder and an outer decoder, and correcting the erasure by inputting the erasure flag ek into the inner decoder and performing erasure compensation in the inner decoder. As the erasure compensation in the inner decoder, channel information is masked while the erasure flag is on. The erasure of data due to a media defect is detected inside the iterative decoder, and the second erasure flag is inputted into the inner decoder to perform erasure compensation in the inner decoder.

Abstract: An information recording and reproducing apparatus which records information on a medium and reproduces information stored on the medium includes a write compensation circuit configured to perform compensation of the information recorded on the medium, wherein the write compensation circuit corrects, in advance, an asymmetry of a signal read from the medium by correcting a write signal in a pulse form along a time axis, and an amount of correction along the time axis is based on information included in the write signal.

Abstract: An information reproducing apparatus which reproduces information recorded on a medium includes an asymmetry correction circuit configured to correct an asymmetry of a signal read from a medium. The apparatus also includes a first high pass filter installed before the asymmetry correction circuit and configured to remove noise in the signal by a first cut-off frequency. The apparatus also includes a second high pass filter installed after the asymmetry correction circuit and configured to remove the noise in the signal by a second cut-off frequency, wherein the second cut-off frequency is higher than the first cut-off frequency.

Abstract: A recording and reproducing apparatus includes an RLL encoder that encodes an information bit string to a code bit string and a RLL decoder that decodes the code bit string to the information bit string. The RLL encoder encodes the information bit string to the code bit string of a run-length-limited code at a high encoding rate satisfying a plurality of conditions of constraint regarding a string of successive zeros. The RLL decoder decodes the code bit string encoded by the RLL encoder to the information bit string.

Abstract: Upon data recording, a data recording unit inserts revise bytes as a predetermined specific code train into at least two or more portions including the head and last portions of data and records the data onto a medium. Upon data reproduction, a data reproducing unit separates a head reproduced signal by using clocks and, thereafter, executes a clock extraction and an amplitude correction by using a signal corresponding to the revise bytes as a specific code train. In principle, an RLL code for the clock extraction and gain tracking is eliminated and, in place of the RLL code, the revise bytes comprising the specific code train are inserted into the data and the data is recorded onto the medium.

Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.

Abstract: A magnetic head testing apparatus includes reference information storing unit for holding a predetermined reference sampling period and a number of reference samplings, sampling unit for sampling reproduced data read a plurality of times from a magnetic medium in the reference sampling period, sampling number acquiring unit for acquiring a sampling number of measured data from a reproduced data base on a sampling result, sampling number ratio calculating unit for calculating a ratio of the sampling number of the measured data and the number of reference samplings, sampling data re-acquiring unit for changing the sampling period of the measured data depending on the calculated ratio and re-acquiring the sampling data and a measured data overlap-displaying unit for overlap-display of the sampling data re-acquired from the measured data a plurality of times.

Abstract: A disk writing apparatus includes: a temperature sensor sensing an ambient temperature of a disk; a sync mark generator generating a sync mark having a pattern when a writing temperature indicating an ambient temperature at which data is written on the disk is sensed, wherein the pattern of the sync mark corresponds to the sensed writing temperature; a writing controller outputting the writing temperature sensed by the temperature sensor to the sync mark generator; a multiplexer adding the sync mark generated by the sync mark generator to the data; and a writing unit writing the data to which the sync mark is added on the disk. Accordingly, error rates when data is written and when data is reproduced can be improved by optimally compensating for the disk writing temperature and the disk reproducing temperature using parameters of devices of an hard disk drive.

Abstract: A timing recovery unit detects a phase offset and a frequency offset from a head area of reproduction data and initially corrects them. The timing recovery unit stores data in which a head reproduction signal has been made to be discrete by a fixed clock into a buffer. A phase offset detector detects the phase offset from the data head area in parallel with the operation for writing the data into the buffer. At the same time, a frequency offset detector detects the frequency offset from the data head area in parallel with the operation for writing the data into the buffer. A correction value of the detected phase offset and a correction value of the detected frequency offset are initially set into a digital PLL. While the data is read out from the buffer, a frequency lead-in and a phase lead-in are executed in the head area.