Patents by Inventor Takashi Akazawa
Takashi Akazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8110900Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.Type: GrantFiled: January 27, 2009Date of Patent: February 7, 2012Assignee: Renesas Electronics CorporationInventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
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Patent number: 8106518Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: GrantFiled: December 17, 2009Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20110280637Abstract: A cleaning device comprises: a rotational brush disposed to touch an image holder and a lubricant, the brush which scrapes the lubricant and applies the scraped lubricant to the image holder, the brush including: a rotational axis; and a plurality of looped bristles disposed around the rotational axis, wherein a contact length of the bristles to the lubricant is longer than a contact length of the bristles to the image holder.Type: ApplicationFiled: May 10, 2011Publication date: November 17, 2011Applicant: KONICA MINOLTA BUSINESS TECHNOLOGIES, INC.Inventors: Kazuteru ISHIZUKA, Takashi AKAZAWA, Daiki YAMANAKA
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Publication number: 20110233773Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: ApplicationFiled: June 6, 2011Publication date: September 29, 2011Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Patent number: 7973415Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: GrantFiled: June 5, 2008Date of Patent: July 5, 2011Assignee: Renesas Electronics CorporationInventors: Michihiro Kawashita, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20110133336Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.Type: ApplicationFiled: February 17, 2011Publication date: June 9, 2011Applicant: Renesas Electronics CorporationInventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
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Patent number: 7897509Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.Type: GrantFiled: June 25, 2010Date of Patent: March 1, 2011Assignee: Renesas Electronics Corp.Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
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Publication number: 20100258948Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Applicant: Renesas Technology Corp.Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
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Patent number: 7759161Abstract: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.Type: GrantFiled: January 27, 2006Date of Patent: July 20, 2010Assignee: Renesas Technology Corp.Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
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Publication number: 20100155940Abstract: In a semiconductor device in which a plurality of semiconductor chips are stacked, performance is enhanced without deteriorating productivity. The semiconductor device has a plurality of elements, an interlayer insulating film, a pad, and a bump electrode electrically connected with the pad sequentially formed on a main surface of a silicon substrate and has a back-surface electrode formed on a back surface of the silicon substrate and electrically connected with the bump electrode. The bump electrode has a protruding portion penetrating through the pad and protruding toward the silicon substrate side. The back-surface electrode is formed so as to reach the protruding portion of the bump electrode from the back surface side of the silicon substrate toward the main surface side and to cover the inside of a back-surface-electrode hole portion which does not reach the pad, so that the back-surface electrode is electrically connected with the bump electrode.Type: ApplicationFiled: December 17, 2009Publication date: June 24, 2010Applicant: RENESAS TECHNOLOGY CORP.Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka Tanaka, Takahiro NAITO, Takashi AKAZAWA
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Patent number: 7738807Abstract: An image forming device including a cleaning member that is made of an elastic material and cleans the surface of the image carrier by contacting with the surface. The drive unit rotates the image carrier in a reverse direction while the cleaning member is contacting with the surface of the image carrier, before the image carrier is rotated in a positive direction for an image formation. The control unit controls the rotation of the image carrier in the reverse direction, in accordance with information indicating a size of a frictional force generated between the cleaning member and the image carrier being rotated.Type: GrantFiled: November 3, 2006Date of Patent: June 15, 2010Assignee: Konica Minolta Business Technologies, Inc.Inventors: Yasuyuki Inada, Takashi Akazawa
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Publication number: 20090309218Abstract: When a through-hole electrode and a rear-surface wire are formed on a rear surface of a chip, a convex portion is formed on the rear surface of the chip due to a rear-surface wiring pad which is a part of the through-hole electrode and the rear-surface wire. This causes the air leakage when the chip is sucked, and therefore, the reduction of the sucking force of the chip occurs. A concave portion is formed in advance in a region where a rear-surface wiring pad and a rear-surface wire are formed. The rear-surface wiring pad and the rear-surface wire are provided inside the concave portion. Thus, a flatness of the rear surface of the chip is ensured by a convex portion caused by thicknesses of the rear-surface wiring pad and the rear-surface wire, so that the reduction of the sucking force does not occur when the chip is handled.Type: ApplicationFiled: June 12, 2009Publication date: December 17, 2009Applicant: RENESAS TECHNOLOGY CORP.Inventors: Michihiro KAWASHITA, Yasuhiro YOSHIMURA, Naotaka TANAKA, Takahiro NAITO, Takashi AKAZAWA
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Publication number: 20090189256Abstract: After forming a ring-shaped trench penetrating through a semiconductor substrate from a rear surface side thereof and forming an insulating film inside the trench and on the rear surface of the semiconductor substrate, a through hole is formed in the insulating film and semiconductor substrate on an inner side of the ring-shaped trench from the rear surface side, thereby exposing a surface protection insulating film formed on a front surface of the semiconductor substrate at a bottom of the through hole. After removing the surface protection insulating film at the bottom of the through hole to form an opening to expose an element surface electrode, a contact electrode connected to the element surface electrode is formed on inner walls of the through hole and opening, and a pad electrode made of the same layer as the contact electrode is formed on the rear surface of the semiconductor substrate.Type: ApplicationFiled: January 27, 2009Publication date: July 30, 2009Inventors: Yasuhiro Yoshimura, Naotaka Tanaka, Michihiro Kawashita, Takahiro Naito, Takashi Akazawa
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Publication number: 20090014843Abstract: A through silicon via reaching a pad from a second surface of a semiconductor substrate is formed. A penetration space in the through silicon via is formed of a first hole and a second hole with a diameter smaller than that of the first hole. The first hole is formed from the second surface of the semiconductor substrate to the middle of the interlayer insulating film. Further, the second hole reaching the pad from the bottom of the first hole is formed. Then, the interlayer insulating film formed on the first surface of the semiconductor substrate has a step shape reflecting a step difference between the bottom surface of the first hole and the first surface of the semiconductor substrate. More specifically, the thickness of the interlayer insulating film between the bottom surface of the first hole and the pad is smaller than that in other portions.Type: ApplicationFiled: June 5, 2008Publication date: January 15, 2009Inventors: Michihiro KAWASHITA, Yasuhiro Yoshimura, Naotaka Tanaka, Takahiro Naito, Takashi Akazawa
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Publication number: 20080079152Abstract: A semiconductor wafer comprising: a tubular trench formed at a position to form a through-hole electrode of a wafer; an insulating member buried inside the trench and on an upper surface of the trench; a gate electrode film and a metal film formed on an upper surface of the insulating member; a multilevel columnar wiring via formed on an upper surface of the metal film; and an external connection electrode formed electrically connected to the metal film via the multilevel columnar wiring via. In this manner, it is unnecessary to have a new process of dry etching to form a through-hole electrode after thinning the wafer and equipment development. Moreover, introduction of a specific design enables formation of through-hole electrodes with significantly reduced difficulties of respective processes.Type: ApplicationFiled: August 10, 2007Publication date: April 3, 2008Applicant: Renesas Technology Corp.Inventors: Naotaka Tanaka, Kenji Kanemitsu, Takafumi Kikuchi, Takashi Akazawa
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Publication number: 20070286636Abstract: An image forming device including a cleaning member that is made of an elastic material and cleans the surface of the image carrier by contacting with the surface. The drive unit rotates the image carrier in a reverse direction while the cleaning member is contacting with the surface of the image carrier, before the image carrier is rotated in a positive direction for an image formation. The control unit controls the rotation of the image carrier in the reverse direction, in accordance with information indicating a size of a frictional force generated between the cleaning member and the image carrier being rotated.Type: ApplicationFiled: November 3, 2006Publication date: December 13, 2007Applicant: Konica Minolta Business Technologies, Inc.Inventors: Yasuyuki Inada, Takashi Akazawa
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Patent number: 7291929Abstract: A connection method is disclosed for a high-performance semiconductor system. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs. Semiconductor chips and the interposer chips are polished by grinding at their rear surfaces, holes are formed at rear surface positions corresponding to external electrode parts on the device side (front surface side) so that the holes extend to front surface electrodes, and metal plating films are applied to the side walls of the holes and rear surface side. Metal bumps of another semiconductor chip laminated at an upper stage being press-fitted into the holes applied with the metal plating films through deformation and being geometrically calked in the through holes formed in the semiconductor chip so as to electrically connected thereto.Type: GrantFiled: January 10, 2006Date of Patent: November 6, 2007Assignee: Renesas Technology Corp.Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
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Publication number: 20060220230Abstract: In order to implement a high-density high-performance semiconductor system small in size, there is provided a method for implementing three-dimensional connection between a plurality of semiconductor chips differing from each other with the shortest metal interconnect length, using penetration electrodes, thereby enabling a fast operation at a low noise level, the method being a three-dimensional connection method very low in cost, and short in TAT in comparison with the known example, capable of bonding at an ordinary temperature, and excellent in connection reliability.Type: ApplicationFiled: January 27, 2006Publication date: October 5, 2006Applicant: Renesas Technology Corp.Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
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Publication number: 20060170112Abstract: A connection method for materializing a high-performance semiconductor system which is small-sized and high dense, is capable to three-dimensionally connecting a plurality of different kinds of semiconductor chips through piercing electrodes with shortest wiring lengths. The connection method enables high-speed operation with low noise, so as to obtain reliable and excellent connection in a short TAT at low costs.Type: ApplicationFiled: January 10, 2006Publication date: August 3, 2006Applicant: Renesas Technology Corp.Inventors: Naotaka Tanaka, Yasuhiro Yoshimura, Takahiro Naito, Takashi Akazawa
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Patent number: 5799527Abstract: A method of producing a stainless steel produces steel sheets having excellent surface brightness. The method includes performing a cold rolling operation using a work roll having a Young's modulus between 25,000 to 70,000 kg/mm.sup.2 in one or more stands of a tandem mill having a plurality of stands. Preferably the work roll is composed of a tungsten carbide based hard metal alloy. The diameter of a work roll at a final stand of the tandem mill is equal to or smaller than a diameter of a work roll in the previous stand. It is preferable that the work roll is dimensioned to have a diameter between 150 mm to 400 mm. In addition, it is preferable that a cold rolling operation is achieved at a reduction between 25% to 60% reduction in the final stand of the tandem mill.Type: GrantFiled: July 24, 1995Date of Patent: September 1, 1998Assignee: Kawasaki Steel CorporationInventors: Kazuhito Kenmochi, Osamu Sonobe, Eisuke Kawazumi, Yoshikazu Seino, Takashi Akazawa, Kazusito Okada