Patents by Inventor Takashi Akioka
Takashi Akioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7982314Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: July 21, 2010Date of Patent: July 19, 2011Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7928952Abstract: An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.Type: GrantFiled: August 22, 2008Date of Patent: April 19, 2011Assignee: Hitachi Displays, Ltd.Inventors: Hajime Akimoto, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
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Publication number: 20100308458Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: July 21, 2010Publication date: December 9, 2010Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7808107Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: May 8, 2009Date of Patent: October 5, 2010Assignees: Renesas Electronics Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20090219069Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: May 8, 2009Publication date: September 3, 2009Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 7547971Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: August 12, 2005Date of Patent: June 16, 2009Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20080316192Abstract: An image display device has a display pixel area having plural pixels arranged in a matrix fashion, plural signal lines for supplying display signal voltages to the pixels, and plural pixel selection lines for selecting pixels from among the pixels to be supplied with the display signal voltages. The pixel selection lines include Y-direction selection lines for selecting rows of the pixels arranged in the matrix fashion and X-direction selection lines for selecting columns of the pixels, and the image display device includes a circuit configuration in which the display signal voltages are supplied from the signal lines to only ones of the pixels each having selected simultaneously both of a corresponding one of the Y-direction selection lines and a corresponding one of the X-direction selection lines.Type: ApplicationFiled: August 22, 2008Publication date: December 25, 2008Inventors: Hajime AKIMOTO, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
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Patent number: 7423623Abstract: An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.Type: GrantFiled: February 23, 2005Date of Patent: September 9, 2008Assignee: Hitachi, Ltd.Inventors: Hajime Akimoto, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
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Patent number: 7254068Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: GrantFiled: March 15, 2006Date of Patent: August 7, 2007Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Publication number: 20060158918Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: ApplicationFiled: March 15, 2006Publication date: July 20, 2006Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Patent number: 7068551Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: GrantFiled: February 1, 2005Date of Patent: June 27, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Publication number: 20060006480Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: August 12, 2005Publication date: January 12, 2006Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Patent number: 6963136Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: GrantFiled: December 17, 2001Date of Patent: November 8, 2005Assignees: Renesas Technology Corporation, Hitachi ULSI Systems Co., Ltd.Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato
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Publication number: 20050151729Abstract: An image display displays image data on an image display part constructed by a display pixel array. In an image display in which image data input means for inputting image data so that the display pixel array has two neighboring areas having different frame rates (>0) is provided or image data is displayed on an image display part constructed by a display pixel array, there is provided image data input means which can input at least one moving image data and at least one still image data into the image display part at different frame rates (>0). A high precision image display can be realized hardly changing a display pixel rewriting speed. A moving image signal output circuit and a still image signal output circuit output image data to the display pixel array, and they are provided as circuit configurations independent of each other.Type: ApplicationFiled: February 23, 2005Publication date: July 14, 2005Inventors: Hajime Akimoto, Mitsuru Hiraki, Hitoshi Nakahara, Takashi Akioka, Yoshiyuki Kaneko, Makoto Tsumura, Yoshiro Mikami
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Publication number: 20050128839Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: ApplicationFiled: February 1, 2005Publication date: June 16, 2005Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Patent number: 6856559Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: GrantFiled: August 11, 2003Date of Patent: February 15, 2005Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Publication number: 20040150055Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.Type: ApplicationFiled: January 22, 2004Publication date: August 5, 2004Applicant: Renesas Technology CorporationInventors: Masao Shinozaki, Takashi Akioka, Kinya Mitsumoto
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Patent number: 6770941Abstract: The invention provides a method of producing a semiconductor device conforming to plural supply voltage specifications without increasing the chip size and the production cost, while the device achieves a high-speed performance. The method includes plural processes for forming plural types of MOS transistors supplied with different power supply voltages in correspondence with external power supply voltages, which are comprised of a first process common to the plural types of MOS transistors, a second process following the first process, which is different by each of the plural types of MOS transistors, and a third process following the second process, which is common to the plural types of MOS transistors.Type: GrantFiled: December 5, 2001Date of Patent: August 3, 2004Assignee: Renesas Technology CorporationInventors: Masao Shinozaki, Takashi Akioka, Kinya Mitsumoto
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Publication number: 20040027896Abstract: Parasitic capacitances formed between bit lines to which signals are to be read out of memory cells and a signal transmission line arranged above them are to be reduced. Second complementary global bit lines for transmitting data read out of memory cells MC via complementary bit lines are arranged above a memory cell array. Each second global bit line is so arranged that a triangle having as its vertexes the center of the section of one of the complementary bit lines, that of the section of the other and that of the section of the second global bit line arranged directly above these complementary bit lines be an isosceles triangle.Type: ApplicationFiled: August 11, 2003Publication date: February 12, 2004Applicants: Hitachi, Ltd., Hitachi ULSI Systems Co. , Ltd.Inventors: Hiroki Ueno, Takashi Akioka, Kinya Mitsumoto, Akihisa Aoyama, Masao Shinozaki
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Publication number: 20040007778Abstract: Circuit elements and wirings constituting a circuit, and first electrodes electrically connected to such a circuit are provided on one main surface of a semiconductor substrate. An organic insulating film is formed on the circuit except for openings on the surfaces of the first electrodes. First and second external connecting electrodes are provided on the organic insulating film. At least one conductive layer for electrically connecting the first and second external connecting electrodes and the first electrodes is placed on the organic insulating film.Type: ApplicationFiled: June 19, 2003Publication date: January 15, 2004Inventors: Masao Shinozaki, Kenji Nishimoto, Takashi Akioka, Yutaka Kohara, Sanae Asari, Shusaku Miyata, Shinji Nakazato